[LLVMdev] Tablegen question
keveman at gmail.com
Tue Jun 9 13:16:39 PDT 2009
> All of the tablegen backends work this way. As you mentioned,
> there are no target-specific tablegen backends at present.
> The underlying observation here is that features are never
> fundamentally "specific for a target". For example, a mapping
> between vector opcodes and associated scalar opcodes could
> reasonably be made on many architectures. Even
> load-balancing between functional units on a processor is a
> target-independent concept, with details like the number and
> nature of the functional units being target-dependent.
Sorry to be such a pest, but I am still trying to understand the usage
model for tablegen. Are you saying it is not a good idea to write a
tablegen backend for something very specific to a target? The examples
I gave happen to be applicable to many targets. But the usage depends
on AN implementation of codegen for a target, no? I mean, I could
choose to put the related scalar instruction in a field with a
specific name in the myInst class in the .td file, and would want to
populate a data structure with a specific name in my C++ code. The
tablegen backend should "know" the names of both the field in the .td
file and the name of the data structure. How can I make this generic?
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