[LLVMdev] Using CallingConvLower in ARM target

[Evan Cheng]

Hi Sandeep,

Dan's idea of adding CC custom lowering support is sound. Can you add  
that support?

Your patch looks good. I look forward to a more complete patch. But I  
do have a nitpick:

Index: include/llvm/CodeGen/CallingConvLower.h
===================================================================
--- include/llvm/CodeGen/CallingConvLower.h	(revision 60966)
+++ include/llvm/CodeGen/CallingConvLower.h	(working copy)
@@ -32,7 +32,8 @@
      Full,   // The value fills the full location.
      SExt,   // The value is sign extended in the location.
      ZExt,   // The value is zero extended in the location.
-    AExt    // The value is extended with undefined upper bits.
+    AExt,   // The value is extended with undefined upper bits.
+    BCnv    // The value is bitconverted in the location
      // TODO: a subset of the value is in the location.
    };

How about BCvt instead of BCnv? Also, please substitue bit-convert for  
bitconvert in comments.

Thanks,

Evan

On Jan 3, 2009, at 11:46 AM, Dan Gohman wrote:

>
> On Dec 27, 2008, at 4:30 AM, Sandeep Patel wrote:
>
>> Attached is a prototype patch that uses CCState to lower RET nodes in
>> the ARM target. Lowering CALL nodes will come later.
>>
>> This patch does not handle f64 and i64 types. For these types, it
>> would be ideal to request the conversions below:
>
> i64 isn't Legal on ARM, so it should already be handled.
>
>>
>>
>> def RetCC_ARM_APCS : CallingConv<[
>> CCIfType<[f32], CCBitConvertToType<i32>>,
>> CCIfType<[f64], CCBitConvertToType<i64>>,
>> CCIfType<[i64], CCExtractElements<2, i32>>,
>>
>> CCIfType<[i32], CCAssignToReg<[R0, R1]>>
>> ]>;
>>
>> The problem is that i64 handling requires splitting into 2 x i32
>> registers. I am not sure how to build CCExtractElements as shown. The
>> current organization of CCState::AnalyzeReturn does not allow for
>> reissuing of the RET with an altered set of operands which is the
>> solution used elsewhere. Can anyone suggest a better way to express
>> this lowering?
>
> One problem with this approach is that since i64 isn't legal, the
> bitcast would require custom C++ code in the ARM target to
> handle properly.  It might make sense to introduce something
> like
>
>    CCIfType<[f64], CCCustom>
>
> where CCCustom is a new entity that tells the calling convention
> code to to let the target do something not easily representable
> in the tablegen minilanguage.
>
> Dan
>
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