[LLVMdev] Early-clobber constraint in TableGen

Jim Grosbach grosbach at apple.com
Tue Dec 15 16:01:33 PST 2009


I've attached a small patch that adds a new early-clobber operand  
constraint option to TableGen and would like to get feedback before  

As background, the ARM store-exclusive instruction (STREX) stores a  
success result code in a register operand, and that register cannot be  
the same register as either the source of the value to be stored, or  
the base address. Specifically.
   STREX Rd, Rm, [Rn]  // Store Rm to the address contained in Rn,  
store zero in Rd if successful, one in Rd if not.
If Rd == Rm or Rd == Rn, the behaviour is undefined.

To model this, we need to be able to specify in the tablegen  
instruction description that Rd is an early-clobber register so that  
the allocator will not use the same register for it as for Rm or Rn.

The syntax is simple:

contraint-list: constraint-list ',' constraint
   | constraint

constraint: '@early' operand
  | operand '=' operand

operand: '$' identifier

MachineIntr::addOperand() checks the target instruction description  
for the constraint when adding register operands and sets  
IsEarlyClobber if it's present.

For a usage example, I've included in the patch the modification to  
use the constraint for the STREX ARM instruction.


Thanks in advance!


-------------- next part --------------
A non-text attachment was scrubbed...
Name: early.patch
Type: application/octet-stream
Size: 5721 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20091215/a1c83dd4/attachment.obj>

More information about the llvm-dev mailing list