[LLVMdev] Back-end with general purpose registers
Micah.Villmow at amd.com
Wed Dec 9 18:35:38 PST 2009
I work on a backend that has very similar constraints, the registers
themselves are type-less as the instruction specifies how to interpret
the bits in the register. After spending countless hours attempting to
get a register class to work with both i32 and f32, I ended up creating
a separate register class for all the data types I wanted to support.
This might not be the most efficient method, but it works and actually
helped me develop the backend faster by removing a lot of problems I was
having with implicit conversions being generated.
For example, one problem I was having when using i32 and f32 in the same
register class and learning LLVM was if I created a node, say add, and
set argument 0 to have a return type of i32 and set argument 1 to a
result that had return type of f32, depending on the return type of the
add instruction, one of the input arguments would implicitly get
converted. Once I split them into separate register classes, LLVM
asserted after every time I did this until I learned everything well
enough that it didn't occur.
I also looked at the X86 approach, but instead of generating different
instructions for the various combinations, I just created instructions
that would load literals/memory into a register first and then I only
needed an instruction for each register class, instead of each register
Hope this helps,
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> On Behalf Of Robert Quill
> Sent: Tuesday, December 08, 2009 7:08 AM
> To: llvmdev at cs.uiuc.edu
> Subject: [LLVMdev] Back-end with general purpose registers
> Hi all,
> I am trying to write a back-end for LLVM where any instruction may
> any type of data. I am looking for the output to be of the format:
> inst.type reg1,reg2
> etc. Where inst is the instruction, e.g. mov and type is data-type
> f32 etc. I tried creating a back-end with a register class which could
> take i32 and f32:
> def GPRegs
> : RegisterClass <"Test",
> [i32,f32], // Formats supported by this class
> 32, // Memory alignment
> [ R0, R1, R2, R3, R4 ]
> And then used this class in the patterns for the instructions.
> I couldn't get this to work as the pattern matcher only considered the
> first type in the list.
> Has anyone ever tried writing a very general back-end like this
> Does anyone have any advice?
> Feel free to ask for more info if I haven't been very clear.
> Thanks for your help,
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