[LLVMdev] Adding multiples-of-8 integer types to MVT

[Ken Dyck]

On Saturday, December 05, 2009 7:34 AM, Duncan Sands wrote,
>
> >> Would there be any interest/opposition to extending the 
> set of simple 
> >> integer types in MVT to include the missing multiples of 8 
> (up to 64 
> >> bits)? That is: i24, i40, i48, i56?
> 
> By the way, the integer type legalization logic should 
> probably go like
> this: let T be an integer type.
> 
> (1) If T is legal, do nothing.
> (2) If there is a legal integer type which is bigger (in 
> bitwidth) than T, then promote T to the smallest legal type 
> which is bigger than T.
> (3) In the remaining case, T is necessarily bigger than the 
> largest legal integer type (call this type L).  Take the 
> smallest positive N such that
>   (bitwidth of T) <= (bitwidth of L) * 2^N If you have 
> equality in the equation, i.e. if the bitwidth of T is a 
> power of two multiple of the bitwidth of L, then expand T 
> into two equal integer types of half the size.  Otherwise 
> promote T to the type with bitwidth equal to the 
> right-hand-side of the equation, i.e. (bitwidth of L) * 2^N.


What would do you think of modifying case (3) slightly as follows?

(3) In the remaining case, T is necessarily bigger than the largest
legal integer type (call this type L).  Take the smallest positive N
such that for some legal type, Leg, 
  
  (bitwidth of T) <= (bitwidth of Leg) * 2^N 

Of the types that satisfy this relation, call the smallest S. If you
have equality in the equation when Leg:=S, i.e. if the bitwidth of T is
a power of two multiple of the bitwidth of the smallest legal type to
which it can be expanded, then expand T into two equal integer types of
half the size.  Otherwise promote T to the type with bitwidth equal to
the right-hand-side of the equation, i.e. (bitwidth of S) * 2^N. 

On a target with 32- and 24-bit registers, for example, this
modification would allow i48 to be expanded directly to 24-bit registers
instead of promoting to an i64 and expanding to 32-bit.

-Ken