[LLVMdev] Selecting Vector Shuffle of Different Types

David Greene dag at cray.com
Wed Dec 2 15:51:56 PST 2009

On Wednesday 02 December 2009 17:46, David Greene wrote:

> VEXTRACTF128_256mri: 	(st:isVoid (vector_shuffle:v4f32 (undef:v8f32),
> VR256:v8f32:$src1, (build_vector)<<P:Predicate_VEXTRACTF128_shuffle_mask>>:
> $src2), addr:iPTR:
> $dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_align
>edstore>> tblgen: In VEXTRACTF128_256mri: Type inference contradiction found
> in node vector_shuffle!
> Well, it's right!  So how do I express this kind of thing?  Since LLVM 2.5
> shufflevector supports creating a vector of a difference size than the
> inputs.  Which is exactly what we need for VEXTRACTF128 and VINSERTF128.

I suppose I could add an extract_subreg to make TableGen happy about types.
This is already custom lowered so it wouldn't be hard to do.  Is that the
correct approach here?


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