[LLVMdev] Problems with DAG Combiner

[Eli Friedman]

On Sun, Aug 23, 2009 at 9:42 AM, Stripf,
Timo<Timo.Stripf at itiv.uni-karlsruhe.de> wrote:
> Hi all,
>
>
>
> i’m writing an back-end for a new research processor architecture and have
> problems with the DAG Combiner. The processor architecture supports i1 and
> i32 registers. 1-bit registers are mainly used as comparison result but
> basic operations like OR are not possible between i1 registers. So I wrote
> custom lowering for i1 OR operations and replaced it by (trunc (or (aext x),
> (aext y))). Now the problem is that the DAG Combiner optimizes it back to an
> i1 OR operations that is not supported by the architecture.
>
>
>
> What is the best way to solve this problem? I take a look at the DAG
> Optimizer and for this OR operation it calls
> DAGCombiner::SimplifyBinOpWithSameOpcodeHands that folds (OP (aext x), (aext
> y)) -> (aext (OP x, y)). No check if the new operation is legal is
> performed.

Sounds like a bug; the DAGCombiner isn't supposed to introduce illegal
operations after operation legalization.

-Eli