[LLVMdev] Error w/ Tablegen + Intrinsics

Villmow, Micah Micah.Villmow at amd.com
Tue Apr 14 19:05:06 PDT 2009

I found the problem



If the intrinsic instructions are not wrapped in:

let Properties = [IntrReadMem] in {



Then they are off by one.


Any reason why this should be required?






From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
On Behalf Of Nate Begeman
Sent: Tuesday, April 14, 2009 6:47 PM
To: LLVM Developers Mailing List
Subject: Re: [LLVMdev] Error w/ Tablegen + Intrinsics


Are you using isTarget = 1 in your intrinsics file?


On Apr 14, 2009, at 6:34 PM, Villmow, Micah wrote:

It seems that Tablegen is generating intrinsic ID's off by  in


In DAGISel.inc, I have the following pattern:

int64_t CN1 = Tmp0->getZExtValue();


    // Pattern: (intrinsic_w_chain:f32 103:iPTR, GPRF32:f32:$src0,
GPRF32:f32:$src1, GPRF32:f32:$src2)

    // Emits: (MACRO_FMA_f32:f32 GPRF32:f32:$src0, GPRF32:f32:$src1,

    // Pattern complexity = 8  cost = 1  size = 0

    if (CN1 == INT64_C(103)) {

      SDValue N2 = N.getOperand(2);

      SDValue N3 = N.getOperand(3);

      SDValue N4 = N.getOperand(4);

      if (N2.getNode()->getValueType(0) == MVT::f32 &&

          N3.getNode()->getValueType(0) == MVT::f32 &&

          N4.getNode()->getValueType(0) == MVT::f32) {

        SDNode *Result = Emit_28(N, AMDIL::MACRO_FMA_f32, MVT::f32);

        return Result;




However, when MACRO_FMA is called, Tmp0->getZExtValue() returns 102!


The section of code where this is probably wrong is:

CodeGenDAGPatterns.cpp:1238 unsigned IID =

Or here:


const CodeGenIntrinsic &getIntrinsicInfo(unsigned IID) const {

    assert(IID-1 < Intrinsics.size() && "Bad intrinsic ID!");

    return Intrinsics[IID-1];



These are the only locations where I can find that it is returning the
IID off by 1.



If someone can let me know what I need to do in order to fix this it
would be greatly appreciated.





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