[LLVMdev] TableGen Enhancement Feasibility

[someguy]

Ok. I just have a vision of this stuff getting 'abused' to acheive odd
things in really really abstract and difficult to grok ways.
KISS?

On Tue, Apr 7, 2009 at 6:03 PM, David Greene <dag at cray.com> wrote:

> On Tuesday 07 April 2009 01:18, someguy wrote:
> > Can you give an example of where you would use such a feature?
> > It seems entirely too abstract (at least to me) at the moment.
>
> Basically I wanted to pass the various prefix encoding classes (XS, XD,
> etc.)
> down into generic SIMD multiclasses so that we could write rr / rm patterns
> once and reuse them with different prefix encoding base classes for the
> various x86 SIMD instruction sets.
>
> These prefix bits are reused in AVX and I found myself duplicating all of
> the
> SIMD boilerplate for AVX that already exists for SSE simply because the
> prefix encoding classes are hard-coded into the SSE classes.
>
> The way I'm going to do this is define some global prefix bits<> and pass
> those instead.  I'll use these just for AVX initially but we can move SSE
> over
> to them and share code going forward.
>
>                                                 -Dave
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20090407/e1425ae1/attachment.html>