[LLVMdev] Determining the register type of a MachineOperand

[Villmow, Micah]

Yes,
 Another reason this is useful is for register-type specific
representations of said register.

For example, all my registers are 128bit vector registers, however, if I
am only dealing with 32 bit vector registers, I can add write/read masks
that tell the underlying hardware not to work on the whole register, but
just a subset of the components.
32bit  scalar mov: mov r1.x___, r0.x000
64bit  scalar mov: mov r1.xy__, r0.xy00
96bit  scalar mov: mov r1.xyz_, r0.xyz0
128bit scalar mov: mov r1, r0

If I had the register type information at code generation time, then I
can use the exact same tablegen pattern for all my register types and
would only need to add the write/read masks in the printer instead of
multiple patterns.

Multiply this by over 100 opcodes and I save A LOT of work. 

-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
On Behalf Of David Greene
Sent: Friday, September 26, 2008 8:39 AM
To: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] Determining the register type of a MachineOperand

On Wednesday 24 September 2008 15:23, Mon Ping Wang wrote:
> To my knowledge, I don't think there is an easy way to get the MVT
> information from a MachineOperand.   Why do you need it for?  In my

See the thread I started on this very topic.  Spilling is one place
you'd like 
to have this information.

> mind, the MachineInstr and its associated operands represent a
> physical machine instruction and I typically want to think of those as
> machine opcodes and machine register files.  I am typically interested
> in the mapping of MVTs to register classes when I'm generating machine
> instructions.  Note that a register class may map to multiple MVTs
> depending on your description.

Right, but the instruction opcode should give a clue about what the bits

represent.  That mapping is what's currently missing.

                                              -Dave
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