[LLVMdev] Multi-Instruction Patterns

[Evan Cheng]

On Sep 24, 2008, at 1:06 PM, David Greene wrote:

>>>
>>
>> As Dan pointed out, #2 is also a workable solution.
>
> Yes, I like Dan's proposal.

Hmmm... Perhaps Dan should implement this. :-)

>
>
>>> What about getting tblgen support for the pattern in the .td file?
>>> That would
>>> be another way to tackle this and would open up a whole bunch of  
>>> other
>>> opportunities.  Instcombine could be entirely expressed as a set of
>>> tblgen
>>> patterns, for example, which is desireable from a maintenance
>>> perspective
>>> and well as new development.  It's much easier to write patterns
>>> than to go
>>> through all of the manual examination that currently exists in
>>> instcombine.
>>
>> I don't think that would work. We still have to model the value as
>> being produced by an instruction. So either we have to select it to a
>> target specific instruction or a target independent instruction (i.e.
>> extract_subreg).
>
> That's right.  The pattern doesn't know if the rest of the vector is  
> going to
> be used elsewhere so we need dataflow information and that implies  
> it needs to
> be done in the coalescer (or some other transformation pass).
>
>> After thinking about this some more, I think #2 is a better solution.
>> Adding XMM0_32 etc. teaches codegen that only lower 32-bits of the
>> registers are used. Perhaps this can open up additional optimization
>> opportunities. On the other hand, adding these registers means
>> introducing more aliasing which has compile time implication.
>
> What about XMM0_64?  What about things like AVX which applies the  
> GPR aliasing
> scheme to vectors?  I think this is the right way to go but we need  
> to do
> things in a comprehensive way so we can expand as needed.

They will be handled the same way. Please file a bug. We'll get to it.

Thanks,

Evan

>
>
>                                                   -Dave
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