[LLVMdev] Generating instruction bundles ?

[Stephane Marchesin]

Hi,

I'm retargetting llvm for a new architecture, basiclaly a target that
has v4f32 registers and a few operations, so it's mostly common stuff.
However, it also has some kind of options on top of the operations,
kinda like VLIW. For example, there is an addition operation, but
there is also a source operand negation bit which you can set. So you
can implement SUB using the ADD opcode (and there is actually no SUB
opcode proper). Besides negating the source operands, there are also
bits to take the absolute value of the source operands as input, bits
to scale the result by power of 2 constants, and bits to do arbitrary
shuffling of the 4 components. Now obviously I'd like to take
advantage of that.

I have taken a look at the ia64 target which has similar requirements,
and seen that it gets around the problem by using an external
optimizing assembler that reorders and packs instructions into
bundles. However since my requirements are so simple I'm hoping I can
do everything inside llvm (and I'm only interested in JIT anyway).

So I guess the question became obvious by now: how can I do this in
llvm? I've been thinking about a couple of solutions:
- Use the tablegen template system to generate all the variants for
eacho operation (with/without absolute value, with/without negation,
with/without post-scaling, with/without all kinds of shuffling, and
all combinations of those). Is this possible ? We're talking about
approximately 70000 variants per instruction here, approximately 300
if we ignore the shuffling which has 256 combinations by itself.
- Use an additional pass that reorders and packs instructions together
(similary to what the ia64 optimizing assembler does), maybe relying
on the instruction scheduler to place the instructions for me.
- Rewrite some of tablegen to support that feature. I'm under the
impression it would be a lot of work for a very specific case, but I
could be wrong here.

Ideas ?

Thanks in advance,
Stephane