[LLVMdev] Multi-Instruction Patterns

[Chris Lattner]

On Sep 23, 2008, at 11:26 AM, David Greene wrote:

> Are there any examples of using tablegen to generate multiple machine
> instructions from a single pattern?  Or do these cases always have  
> to be
> manually expanded?

PPC has a bunch of examples, for example:

// Arbitrary immediate support.  Implement in terms of LIS/ORI.
def : Pat<(i32 imm:$imm),
           (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;

// ADD an arbitrary immediate.
def : Pat<(add GPRC:$in, imm:$imm),
           (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
// OR an arbitrary immediate.
def : Pat<(or GPRC:$in, imm:$imm),
           (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
// XOR an arbitrary immediate.
def : Pat<(xor GPRC:$in, imm:$imm),
           (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;


-Chris