[LLVMdev] Question on use of subregs
christopher.lamb at gmail.com
Sat Mar 15 20:19:43 PDT 2008
Fair warning, this area of the code generator is under active
Take a look at how the x86-64 backend models the implicit sign
extending using 'subreg_to_reg' in the X86Instr64bit.td file.
On Mar 15, 2008, at 9:42 AM, Bagel wrote:
> Thanks, I seem to have gotten sub-registers to work. I can't seem
> to suppress
> the zero-extend sometimes. There is no need to explicitly zero
> extend bytes to
> words on this machine as all byte operations do that.
> I have also gotten some memory-to-memory to work.
> Evan Cheng wrote:
>> On Mar 14, 2008, at 10:17 AM, Bagel wrote:
>>> I'm trying to write a backend for a machine that has both byte and
>>> instructions. Both varieties of instructions operate on the same
>>> set of
>>> general registers. A byte mode instruction on a general register
>>> always clears
>>> the upper bits. Register-to-register byte mode and work mode
>>> instructions set
>>> condition codes based on bytes and words and thus are not
>>> Do I need to have separate classes of registers for the work and
>>> instructions? If so, I assume the byte registers are declared as
>> Yes. Then you want to declare byte registers as sub-registers of the
>>> Also, this machine supports memory-to-memory operations in byte and
>>> flavors. What do I need to look out for to support this.
>> The instruction selector can be taught to *fold* loads and stores.
>> has many load + modify + write instructions. You can take a look
>> patterns in X86InstrInfo.td Does the target have operations that
>> operate on multiple memory operands? In theory, it's possible to
>> patterns to select these as well.
>>> If have looked at the X86 *.td's, but that architecture is so
>>> complex it is
>>> hard to extract the information I need.
>> Unfortunately x86 is the only target that supports both of the
>> features you described. If you want to get started by looking at
>> existing examples, it's pretty much the only choice.
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>>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
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