[LLVMdev] Question on use of subregs

Bagel bagel99 at gmail.com
Fri Mar 14 10:17:15 PDT 2008

I'm trying to write a backend for a machine that has both byte and word 
instructions.  Both varieties of instructions operate on the same set of 
general registers.  A byte mode instruction on a general register always clears 
the upper bits.  Register-to-register byte mode and work mode instructions set 
condition codes based on bytes and words and thus are not interchangeable.

Do I need to have separate classes of registers for the work and byte 
instructions?  If so, I assume the byte registers are declared as SubRegs?

Also, this machine supports memory-to-memory operations in byte and word 
flavors.  What do I need to look out for to support this.

If have looked at the X86 *.td's, but that architecture is so complex it is 
hard to extract the information I need.


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