[LLVMdev] Vector cast

[Nicolas Capens]

Hi Eli,

Great to hear this is actively being worked on. Aside from reporting
potential bugs is there anything specific I could look at to help out?

Thanks for the advice on using natively available operations. Unfortunately,
this doesn't really work when aiming to support multiple targets. Anyway I
understand that workarounds will remain to be necessary for some time.

Cheers,

Nicolas


-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On
Behalf Of Eli Friedman
Sent: Sunday, 22 June, 2008 02:19
To: LLVM Developers Mailing List
Subject: Re: [LLVMdev] Vector cast

On Sat, Jun 21, 2008 at 4:24 PM, Nicolas Capens <nicolas at capens.net> wrote:
> I seem to be unable to cast a vector of integers to a vector of floats
> (uitofp [4 x i8] to [4 x float], to be exact). It hits an assert in
> LegalizeDAG.cpp line 5433: "Unknown int value type". The Assembly Language
> Reference Manual's definition of uitofp doesn't indicate that this is
> unsupported, so it looks like a bug to me. I'm on an x86 system by the
way.

I assume you mean something like "uitofp <4 x i8> %0 to <4 x float>"?
It's supposed to be supported, I think, but that sort of thing isn't
reliable at the moment. AFAIK, baldrick is working on a replacement
for LegalizeDAG that should handle that sort of thing better.

In the meantime, the following should perform the operation you want
efficiently on X86:
define <4 x float> @charvectofloatvec(i32) nounwind {
insertelement <4 x i32> undef, i32 %0, i32 0
bitcast <4 x i32> %2 to <16 x i8>
shufflevector <16 x i8> %3, <16 x i8> zeroinitializer, <16 x i32> <i32
0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20,
i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
shufflevector <16 x i8> %4, <16 x i8> zeroinitializer, <16 x i32> <i32
0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20,
i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
bitcast <16 x i8> %5 to <4 x i32>
sitofp <4 x i32> %6 to <4 x float>
ret <4 x float> %7
}

At least for the moment, the trick to getting high-quality,
predictable output for vector operations in LLVM is to make sure the
operations are natively available on the underlying architecture...
note that all the operations here directly map to a single X86
instruction. The backend is getting smarter, but it'll be a while
before it's really good at generating high-quality vector code.

-Eli
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