[LLVMdev] VFCmp failing when unordered or UnsafeFPMath on x86

Nicolas Capens nicolas at capens.net
Mon Jun 16 03:23:16 PDT 2008

Hi Chris,


I've attached a replacement of fibonacci.cpp that reproduces the issue on
x86/SSE systems.


Regarding the definition of the VFCmp instruction, I think it would really
be a lot more valuable to define it as returning all 1's or all 0's per
element. Just setting the most significant bit is pretty much worthless
(someone correct me if I'm wrong). I checked and I couldn't actually find
any instruction set that only sets the MSB when comparing vectors, except by
actually doing just a subtract. Since people need full masks before they can
do anything useful with it (requiring a shift or conditional replace) I was
thinking why not make that part of VFCmp? Note that this change in VFCmp's
definition won't break compatibility.


Kind regards,




From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On
Behalf Of Chris Lattner
Sent: Saturday, 14 June, 2008 02:40
To: LLVM Developers Mailing List
Subject: Re: [LLVMdev] VFCmp failing when unordered or UnsafeFPMath on x86



On Jun 13, 2008, at 12:27 AM, Nicolas Capens wrote:

Hi all,


When trying to generate a VFCmp instruction when UnsafeFPMath is set to true
I get an assert "Unexpected CondCode" on my x86 system. This also happens
with UnsafeFPMath set to false and using an unordered compare. Could someone
look into this?


Please provide a testcase.


While I'm at it, is there any reason why only the most significant bit of
the return value of VFCmp is defined (according to the documentation)? Both
AltiVec and SSE set the components of the result to either all 1's or all
0's. Having only the most significant bit doesn't seem useful to me at all,
and (arithmetic) shifting vectors to replicate the bit isn't supported.


LLVM is intended to support other vector instruction sets, including SPU,
Alpha, etc.  The commonality was that the MSB is set, and we would like to
add support for vector shifting at some point.



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