[LLVMdev] Regarding ARM CodeGen

[kapil anand]

Hi all,

I am using LLVM compiler and CodeGen  for generating ARM binaries.

I was going through the code for ARM backend. I noticed that the ARM
Condition field( Bits 31-28) is generated by converting the conditions used
in icmp and branch. For example, if I have following C Code

int a,b,c,d;
c = a+b;

if(c==0)
     d = a + 10;


Then I get ( Assembly Instructions with opcodes only)

add
*cmp*
addeq


( basically converting branch to the predicate condition field)

I have a few questions regarding the above operation.
1. If I use GCC on above code, then I get following .s output:
   adds
   addeq

I don't  get the intermediate compare instruction, which I got when I used
LLVM. So, does LLVM ARM Backend assume that only "cmp" and "test"
instructions can set the Status flags and not the usual arithmetic
instructions. Is there any way of specifying to Backend that add can also
modify status flag through "s" bit.

2. Also, when I looked at ISelLowering file, I noticed that conditions used
in "icmp" instructions are converted to ARM Predicate Condition fields. Icmp
has only "10" conditions, which map to corresponding "10" conditions in ARM
Condition field but ARM can have fourteen conditions. If we consider the
mapping shown in ISelLowering File, then following four conditions are left:
"VS": Overflow Set
"VC" : Overflow Clear
"MI" : Minus
"PL": Plus

So, does this mean that it is not possible to obtain the above conditions
are predicate if we use LLVM Compiler framework.

Thanks

Regards,
Kapil Anand
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