[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC

[Evan Cheng]

Hi Gary,

The patch looks great. But I do have one comment:

+let usesCustomDAGSchedInserter = 1 in {
+  let Uses = [CR0] in {
+    let Uses = [R0] in
+    def ATOMIC_LOAD_ADD_I32 : Pseudo<

The "let Uses = [R0]" is not needed. The pseudo instruction will be  
expanded like this later:

+    BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
+      .addReg(ptrA).addReg(ptrB);
+    BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0)
+      .addReg(incr).addReg(dest);
+    BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
+      .addReg(PPC::R0).addReg(ptrA).addReg(ptrB);

The second instruction defines R0 and the 3rd reads R0 which is enough  
to tell the register allocator what to do.

I do have a question, must it use R0? If it's not fixed, it's probably  
better to create a new virtual register and use that instead.

Thanks,

Evan

On Jul 2, 2008, at 8:29 AM, Gary Benson wrote:

> Evan Cheng wrote:
>> You need to insert new basic blocks and update CFG to accomplish  
>> this.
>> There is a hackish way to do this right now.  Add a pseudo  
>> instruction
>> to represent this operation and mark it usesCustomDAGSchedInserter.
>> This means the intrinsic is mapped to a single (pseudo) node. But it
>> is then expanded into instructions that can span multiple basic
>> blocks. See PPCTargetLowering::EmitInstrWithCustomInserter().
>
> How does this look?  It's a big patch, but it basically does this:
>
> - Adds ATOMIC_LOAD_ADD, ATOMIC_CMP_SWAP and ATOMIC_SWAP nodes,
>   and ATOMIC_LOAD_ADD_I{32,64}, ATOMIC_CMP_SWAP_I{32,64} and
>   ATOMIC_SWAP_I{32,64} pseudo-instructions with custom inserters.
>
> - Replaces L[WD]ARX and ST[WD]CX pseudo-instructions with the
>   actual PPC instructions they represent.
>
> - Removes CMP_UNRESERVE nodes and CMP_UNRES[wd]{,i} pseudo-
>   instructions.
>
> Cheers,
> Gary
>
> -- 
> http://gbenson.net/
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