[LLVMdev] llvm.atomic.barrier implementation

[Andrew Lenharth]

On 2/15/08, Chris Lattner <sabre at nondot.org> wrote:
> GCC 4.2 compiles this to a no-op on x86:
>
>  void foo() {
>    __sync_synchronize();
>  }
>
>  Are you seeing different behavior?  What am I missing here?

I see the same.  I don't know why, __sync_synchronize() is suppose to
be a full memory barrier.  I don't know why gcc doesn't generate a
barrier on x86.  It does on alpha.  X86 will do load-load reordering,
so I would expect a "full memory barrier" primitive in gcc to actually
generate a barrier (and at least the linux kernel implements barriers
on x86 for hardware io).  In any event, generating the intrinsic all
the time should keep the optimizations from reordering when the
programmer doesn't want them too, and the codegen for x86 can always
remove unnecessary barriers.

Andrew