[LLVMdev] Using CallingConvLower in ARM target

[Sandeep Patel]

Attached is a prototype patch that uses CCState to lower RET nodes in
the ARM target. Lowering CALL nodes will come later.

This patch does not handle f64 and i64 types. For these types, it
would be ideal to request the conversions below:

def RetCC_ARM_APCS : CallingConv<[
  CCIfType<[f32], CCBitConvertToType<i32>>,
  CCIfType<[f64], CCBitConvertToType<i64>>,
  CCIfType<[i64], CCExtractElements<2, i32>>,

  CCIfType<[i32], CCAssignToReg<[R0, R1]>>
]>;

The problem is that i64 handling requires splitting into 2 x i32
registers. I am not sure how to build CCExtractElements as shown. The
current organization of CCState::AnalyzeReturn does not allow for
reissuing of the RET with an altered set of operands which is the
solution used elsewhere. Can anyone suggest a better way to express
this lowering?

Deep

On Fri, Dec 19, 2008 at 6:43 PM, Sandeep Patel <deeppatel1987 at gmail.com> wrote:
> On Fri, Dec 19, 2008 at 4:54 PM, Evan Cheng <evan.cheng at apple.com> wrote:
>>
>> On Dec 18, 2008, at 7:05 PM, Sandeep Patel wrote:
>>
>>> Since there have been no answers, I will have to start at the
>>> beginning.
>>>
>>> One of the first changes I'd like to try is adding the additional
>>> registers and the AAPCS VFP variant calling conventions. Is there a
>>> reason why the ARM Target isn't using the CCState machinery?
>>
>> Please clarify. I am not sure what you mean by CCState machinery.
>
> The ARM Target doesn't use the class CCState. For example,
> CCState.AnalyzeCallOperands, CCState.AnalyzeCallReturn,
> CCState.AnalyzeReturn, etc. There is no ARMCallingConv.td as there is
> for other targets. All calling convention decisions are made manually.
>
> If there is no reason not to, it might simplify adding the AAPCS
> Standard Variants like AAPCS-AFP, etc. since they'll be defined with
> TableGen and therefore more readily extended.
>
>> Evan
>>
>>>
>>>
>>> Deep
>>>
>>> On Fri, Dec 5, 2008 at 5:22 PM, Sandeep Patel
>>> <deeppatel1987 at gmail.com> wrote:
>>>>
>>>> Is anybody actively working on additional ARM target support?
>>>>
>>>> I need Cortex support (ARMv7, VFPv3, and Neon).
>>>>
>>>> Thank you.
>>> _______________________________________________
>>> LLVM Developers mailing list
>>> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>>
>> _______________________________________________
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>>
>
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