[LLVMdev] Alias analysis and instruction level parallelism

[Devang Patel]

On Apr 2, 2008, at 1:14 AM, Pertti Kellomäki wrote:

> I am pretty excited about the recent activity on dependence
> analysis. The only remaining problem from our point of view
> is how to get the alias information to the back end instruction
> scheduler. If I understand things correctly, the alias information
> basically gets lost in the process of lowering to target
> instructions.
>
> We are interested in the DSP domain, so we really need to get
> SIMD style parallelism to work, and this needs alias information.

If you handle this at LLVM IR level then you've access to all the  
alias info and GEP instructions are directly available to you.  LLVM  
IR supports vector types for SIMD style parallelism and target  
specific code generators lowers them appropriately.

-
Devang

>
> In one of the earlier threads on alias analysis someone commented
> that preserving the alias information would not really be that
> difficult, but possibly tedious.
>
>
> My initial reaction is that if one were to decorate MachineInstr's
> with the LLVM level pointer values that they use for reading
> and writing memory, then one should be able to use those
> values and the AliasAnalysis interface to query dependences
> between MachineInstr's. I am not intimately familiar with
> how the lowering is done, so if there are some obvious
> problems with this approach, please let me know.
> -- 
> Pertti
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