[LLVMdev] Alias analysis and instruction level parallelism

Pertti Kellomäki pertti.kellomaki at tut.fi
Wed Apr 2 01:14:03 PDT 2008

I am pretty excited about the recent activity on dependence
analysis. The only remaining problem from our point of view
is how to get the alias information to the back end instruction
scheduler. If I understand things correctly, the alias information
basically gets lost in the process of lowering to target

We are interested in the DSP domain, so we really need to get
SIMD style parallelism to work, and this needs alias information.
In one of the earlier threads on alias analysis someone commented
that preserving the alias information would not really be that
difficult, but possibly tedious.

My initial reaction is that if one were to decorate MachineInstr's
with the LLVM level pointer values that they use for reading
and writing memory, then one should be able to use those
values and the AliasAnalysis interface to query dependences
between MachineInstr's. I am not intimately familiar with
how the lowering is done, so if there are some obvious
problems with this approach, please let me know.

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