[LLVMdev] a possible alternative for pre-legalize extended ValueTypes

[Dan Gohman]

On Fri, Jun 22, 2007 at 11:57:27AM -0700, Christopher Lamb wrote:
> 
> On Jun 22, 2007, at 11:06 AM, Dan Gohman wrote:
> 
> >If we can assume that vector lengths will always be a fixed  
> >multiple of 2,
> >we can encode vector lengths for extended vector types as the log2  
> >of the
> >length, biased by one. Using only 6 bits gets us vector lengths up to
> >(2**64)-2, which Ought To Be Enough For Anyone.
> 
> Yerk! This would throw a serious wrench in supporting non power of  
> two vector lengths, which is needed by us. We needed to add v3f32 and  
> v3i32 ValueTypes just to define our register file in the .td.

Ok. You'll probably want to have dedicated simple values for vector types
which are legal, and those would still fit within the initial 5 (or maybe
6) bits. But then you may want to do things like v6f32 and so on, so
you'll still need more flexibility than the log2 encoding.

I'm ok with a linear encoding for extended vector lengths. I don't know
offhand how many bits will be needed for it, so I don't know how many
bits that leaves for arbitrary bitwidth integers and such, but this may
be a situation where we shouldn't worry it until someone actually wants
to do it.

Dan

-- 
Dan Gohman, Cray Inc.