[LLVMdev] PR1350 (Vreg subregs) questions

Christopher Lamb christopher.lamb at gmail.com
Tue Jun 12 18:25:06 PDT 2007


On Jun 12, 2007, at 10:53 AM, Chris Lattner wrote:

> On Tue, 12 Jun 2007, Christopher Lamb wrote:
>>>>  What's the best way to get an SDNode through to DAG scheduling
>>>>  without getting mangled during Lowering/ISel?
>>>
>>>  What do you mean by "mangled"? Please clarify.
>>
>> My mangled I mean the nodes shouldn't be isel'ed into anything  
>> else because
>> they need to survive through to scheduling. Is there a preferred  
>> means of
>> having those nodes skipped during selection and lowering?
>
> You'll have to teach legalize and isel about these nodes, just like  
> they
> know about ISD::Register nodes.  subregs will be a new first-class  
> node
> type that all of the dag stuff will have to know about (at least to  
> pass
> them through).

Great! Found the spot to do that.

>
>>>>  When should subregs be flattened to actual registers: AsmPrinter?
>>>>  Somewhere in LiveIntervals, during RegAlloc?
>
> This should definitely be done during regalloc.

It seems that LiveIntervals will need to be taught about the new form  
of virtual registers. Hrm. I'm going to try to break this work up as  
much as possible.

Also, do you see any problems with using the following class for  
vregs? It makes it possible to not have to go through and update  
every call site for a large number of functions.

class vreg : public std::pair<unsigned,unsigned> {
public:
   vreg(unsigned f) : std::pair<unsigned,unsigned>(f, 0) {}
};

If this definition is OK, where should it live? It's needed all over  
the place...

--
Christopher Lamb



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