[LLVMdev] PR1350 (Vreg subregs) questions

Christopher Lamb christopher.lamb at gmail.com
Mon Jun 11 18:14:55 PDT 2007


What's the best way to get an SDNode through to DAG scheduling  
without getting mangled during Lowering/ISel?

When should subregs be flattened to actual registers: AsmPrinter?  
Somewhere in LiveIntervals, during RegAlloc?

Is there are common API used to turn vregs into physregs that could  
be changed to flatten any subregs in a central location?
--
Christopher Lamb






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