[LLVMdev] Segment Register Use

[Wilfred L. Guerin]

I realize I am one of the few who uses the segment registers
(especially CS and DS) on the ia32 chips for example, and a definite
few with complete segregation models that rival specialized physical
processors...

GCC still fails to use these correctly and if your LLVM still depends
on either Generic or some of the RTL models they use in various
processor definitions, I express concern for optimization and
compilation.

Please at least hint that you intend to optimize and compile using all
functionality of the processor; gcc compiles to binaries 2-3x slower
in many projects due to this assinine problem historicly.

In the machines with far more advanced registers, this is debilitating.

Please inform.

-Wilfred
WilfredGuerin at gmail.com