[LLVMdev] Proposal for atomic and synchronization instructions

[Christopher Lamb]

On Jul 9, 2007, at 10:33 AM, Scott Michel wrote:

> Torvald Riegel wrote:

>> What are the reasons because of which you picked the Load/Store  
>> model for
>> barriers and not some other kind (e.g., acquire/release/...)?
>
> Chandler looked at what the various current LLVM architectures and
> summarized what he found. What he found are the memory barriers  
> that the
> various processors support.

That being said, it probably would not be difficult to add an  
optional pointer to the membarrier instructions. Thus one could map  
acquire/release semantics onto the membarrier, and it would be up to  
the various optimizations to conservatively determine whether code  
motion is legal given aliasing information.

--
Christopher Lamb



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