[LLVMdev] Pattern matching questions

[Scott Michel]

I was able to resolve my previous question about dealing with custom
loads/stores, and following Chris' suggestion, the IBM Cell SPU backend
can generate code for "int main(void) { return 0; }" without crashing
llc. There's a lot of work still to be done... like getting frame
offsets correctly computed and hauling in the raft of intrinsics that
the Cell SDK defines.

Three quick questions:

- How does one deal with multiple instruction sequences in a pattern?
  To load a constant is a two instruction sequence, but both
  instructions only take two operands (assume that r3 is a 32-bit
  register):

  ilhu $3, 45             # r3 = (45 << 16)
  iohl $3, 5              # r3 |= 5

  I tried:

  def : Pat<(i32 imm:$imm),
            (IOHL (ILHU (HI16 imm:$imm)), (LO16 imm:$imm))>;

- The return instruction for Cell SPU is "bi $lr". How do I jam that
  into the instruction info w/o tblgen bitching up a storm about the
  "$" or the extra "bi" operands?

- Immediates in a pattern: To move one register to another involves
  using the 3-operand OR instruction, but how do I encode an immediate
  w/o a type inference contradiction?

  def : Pat<(set R32C:$rDest, R32C:$rSrc),
            (ORIr32 R32C:$rSrc, 0)>;

Thanks for the clue!