[LLVMdev] Register Alias Sets

[Anton Vayvod]

On 4/7/07, David Greene <greened at obbligato.org> wrote:
>
> I notice that in X86GenRegisterInfo.inc, the AliasSets do not
> include the register being queried.  For example:
>
>   const unsigned RAX_AliasSet[] = { X86::EAX, X86::AX, X86::AL, X86::AH,
> 0 };
>   const unsigned EAX_AliasSet[] = { X86::RAX, X86::AX, X86::AL,
> X86::AH, 0 };
>
> This makes it hard to do set comparisons.  RAX and EAX really have
> equivalent alias sets but one wouldn't know that from these definitions.


Sure, but where these comparisons are needed, for example? RAX and EAX alias
sets intersect and that's enough to decide that these regs can't be assigned
simultaneously. In general, that what you would check anyway because for
some architectures you won't (theoretically, AFAIK) have equal alias sets at
all, but they'll intersect. Consider the following example (as I remember it
from some paper on representing irregular architechtures):
 There are 8 32-bit general purpose registers (R0-R7) and there are 7 64-bit
registers (W0-W6). Ri reg is a high word of Wi and R(i+1) is a low word of
Wi (i runs from 0 to 6). So the alias set for Wi is { Ri, R(i + 1)} (you can
include Wi, of course). You can't allocate neighbouring W-regs the same time
as their alias sets intersect (but not equal).

Also consider saving space and one another minimalism issue: why return
the queried reg in its alias set if you already know it?

Is there a specific reason that these registers are left out?  Would
> things seriously break if they were added in?


I think, that is how alias sets are more comfortable to use (at least in the
existing LLVM code). Usually, one does smth special with one register and
some other thing for every aliased reg. Probably, register allocator would
be broken or at least there would be one unnecessary action each time smth's
done with alias set. For example, when you set some reg being used via a
PhysRegTracker object, it automagically checks for every aliased reg and
marks it being used, too. If the queried reg was included,
PhysRegTracker could mark the specified reg twice and so on. Though the
changes necessary to handle this don't seem too difficult at first glance.

I know RegAllocLinearScan.cpp does some checks for register aliasing
> by looking for empty AliasSets.  I imagine that'll get us into trouble.


Probably. As I already said it'd get us into a little overhead on each alias
set operation (I mean without modifying its code, of course). I believe
other allocators check alias sets as well (indirectly, may be).

However, I'm only a user of LLVM's target definitions. May be, someone'll
give you more presice, correct and complete answer.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20070407/4692c22e/attachment.html>