[LLVMdev] Implicit defs
romixlev at yahoo.com
Sat Oct 14 17:45:50 PDT 2006
Thanks for your response.
> On Sat, 14 Oct 2006, Roman Levenstein wrote:
> > Is it possible to dynamically define implicit defs for some
> > instructions?
> Yes! This is what explicit operands are :). Specifically, if you
> want to
> vary on a per-opcode basis what registers are used/def'd by the
> instruction, you can just add those registers as explicit use/def
> in the machine instruction with the physical registers directly
> filled in.
OK. I have not explained in my first email about DEFs everything I
wanted, the second one was a bit more specific ;) Of course, I realize
that I can add explicit DEFs to the machine instruction. But is it
possible to do it at the higher level, e.g. in the ISelLowering passes,
where no machine insns are generated yet. Basically, it is currently
possible at this level to do the mapping of virtual registers for
parameters to the physical registers, and this can be done without any
problems. It is usually done in LowerCALL or something like that. I'd
like to do the same for return registers at the same place, to keep all
these related things together and because of certain symmetry of goals.
But if I would do it as you propose, I'll need to put somewhere else,
where we can operate at the MI level, right? So the question is
actually about possibility of doing it in LowerCALL, where MIs are not
P.S. Chris, have you seen this mail from me on the mailing list?
There was no reply, so I'm not sure if it is because there are no
comments or may be because it was overseen.
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