[LLVMdev] [RFC, ARM] expanding RET to CopyToReg;BRIND
sabre at nondot.org
Tue May 30 11:08:57 PDT 2006
On Tue, 30 May 2006, [UTF-8] Rafael Esp?ndola wrote:
> I have changed the way in which the ARM backend generates a function
> return. Instead of expanding a RET to a CopyToReg;RETFLAG, it now
> expands into a CopyToReg;BRIND. I haven't commit it yet, but the patch
> is attached.
Ok, I haven't looked at the code, but you're free to do whatever make
> In my opinion the resulting code is easier to understand, but I have
> some questions:
> Why all backends use RETFLAG?
The backends seem to be doing the following:
1. For 'ret void', a "ISD::RET" node is left along and not lowered. As
such, it gets directly pattern matched. On PPC, for example, we have:
// Return void support.
def : Pat<(ret), (BLR)>;
... which maps it directly to the PPC "blr" instruction.
2. For 'ret value', the targets custom lower the ISD::RET node into some
number of CopyToReg nodes (to set up the live outs), then need a node
to represent the return. The return node has to be flagged do the
copies, so that the scheduler doesn't make the copies wander from the
> Why it is named RETFLAG?
Historical reason. Originally we didn't have nodes that could
*optionally* have an input flag. A better design, e.g. on PPC would be to
have a PPCISD::RET node, which takes an optional input flag, and always
lower RET to it.
> Why the Copy that places the result must have a Flag operand? If I
> understand correctly, the Flag operand exists in nodes that use a flag
> register (cpsr in ARM).
Flag in the SelectionDAG stuff is so named because it was originally used
for condition codes. However, it has since grown to mean "keep these two
nodes always together". In the case of return, you want the scheduler to
produce code like this (on PPC):
R3 = outval_virtreg
not like this:
R3 = outval_virtreg
So the copy and blr are flagged together.
Another case where flags are useful are for things like the X86 variable
shift instruction. There the shift amount is required to be in the CL
register, so we generate code like this:
CL = shamt_virtreg
X = shl Y, CL
We don't want the copy and shift to wander apart from each other (e.g. we
don't want another shift to get scheduled in between them), so we flag
them together. In practice, these copies usually get coallesced away.
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