[LLVMdev] matching "ret 0"

Rafael EspĂ­ndola rafael.espindola at gmail.com
Tue May 16 18:18:56 PDT 2006

I am trying to make the ARM backend compile

int f() {return 0;}

I have added a custom expansion of ret that is similar to the one used
in ppc and sparc. If I understand it correctly, it will expand the ret
into an assignment to the return register (R0) and a RETFLAG node.

I declared the bx instruction to match RETFLAG.

Now the instruction selection says it can't match "
i32 = Constant <0>"

I tried to declare a fake mov that is capable of moving arbitrary i32
constants to a register (ops IntRegs:$dst, i32imm:$src). But the error
is still the same.

Does anyone has a suggestion on what the problem might be? Or any tips
for debugging instruction selection?


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