[LLVMdev] need some help to remove a dummy mov
sabre at nondot.org
Thu Aug 3 10:36:38 PDT 2006
On Thu, 3 Aug 2006, [UTF-8] Rafael Esp?ndola wrote:
> It would be better to do a "mov r0, #42" directly. The isel dag is
> almost identical to the one generated for ppc32, but on ppc32 "li r3,
> 42" is used.
> I have checked that isMoveInstr returns true for the "mov r0,r 4".
> Does someone has any idea why the additional mov is generated?
This looks like a scheduling problem. Looking at the -print-machineinstrs
dump, the input to the register allocator looks like this:
# Machine code for g():
Live Outs: R0
entry (0x8b030c0, LLVM BB @0x8b00350):
%reg1024 = movri 42
%R0 = movrr %reg1024
The problem is that 'bl' clobbers R0/R1/R2/R3, so "reg1024" can't get any
of those. As such, it gets allocated to R4.
If you use one of the 'register pressure reducing' schedulers, you get
good code, e.g.:
$ llvm-as < t.ll | llc -march=arm -sched=list-burr
sub r13, r13, #4
str r14, [r13]
mov r0, #42
ldr r14, [r13, #0]
add r13, r13, #4
To default to "reducing register pressure", add this:
to your ARMTargetLowering ctor, like the X86 backend has.
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