[LLVMdev] Intel vs. AT&T Assembly.
sabre at nondot.org
Sun Apr 30 20:19:13 PDT 2006
On Sat, 29 Apr 2006, Jeff Cohen wrote:
> We know. Someone offered to do the Intel version, but did little more than a
> huge cut and paste of the AT&T version and then lost interest. No one else
> has had the time or inclination to finish the (barely begun) job. Patches
> accepted :)
Actually, that's not true. The LLVM X86 backend started out emitting
intel mode for use with GAS and it's "intel syntax mode" (which does use
registers with %'s). Unfortunately GAS has (or commonly available
versions have) a number of bugs in intel syntax mode (e.g. you can't
define a function named 'dword'), so we switched to using AT&T syntax.
Intel syntax mode was retained because it's nicer to read :), and because
it may be useful in the future. As Jeff says, patches are welcome to make
it do something useful, e.g. be assemblable with MASM or NASM.
> Ralph Corderoy wrote:
>>> It's a long way towards it:
>>> # AT&T. # Intel.
>>> .text .text
>>> .align 16 .align 16
>>> .globl main .globl main
>>> .type main, @function
>>> main: main:
>>> subl $12, %esp sub esp, 12
>>> fnstcw 10(%esp) fnstcw word ptr [esp + 10]
>>> movb $2, 11(%esp) mov byte ptr [esp + 11], 2
>>> fldcw 10(%esp) fldcw word ptr [esp + 10]
>>> movl 20(%esp), %eax mov eax, dword ptr [esp + 20]
>>> movl 4(%eax), %eax mov eax, dword ptr [eax + 4]
>> Whoops. I've provided my post-processed version of lli's Intel output
>> which, since I removed the `%' and lowered the `DWORD PTR' isn't a good
>> example. Still, you get the gist; there are already significant
>> differences between the two.
>> LLVM Developers mailing list
>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
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