[LLVMdev] avoid live range overlap of "vector" registers

[Chris Lattner]

On Fri, 6 May 2005, Tzu-Chien Chiu wrote:
> a "vector" register r0 is composed of four 32-bit floating scalar
> registers, r0.x, r0.y, r0.z, r0.w.
>
> each scalar reg can be assigned individually, e.g.
>
>  mov r0.x, r1.y
>  add r0.y, r1,x, r2.z
>
> or assigned simultaneously with vector instructions, e.g.
>
>  add r0.xyzw, r1.xzyw, r2.xyzw
>
> My question is how to define the register in .td file to avoid the
> code generator overlaps the live ranges of vector registers?

If you want to access each part individually, I would suggest doing the 
tedious thing and including them all.  The IA64 backend has 3*128 
registers, so there is precedent for this...

-Chris

> i could define a 'definition' for each scalar register, but it's tedious:
>
>
> class FooReg<string n> : Register<n> {}
>
> def r0_x: FooReg<"r0.x">;
> def r0_y: FooReg<"r0.y">;
> def r0_z: FooReg<"r0.z">;
> def r0_w: FooReg<"r0.w">;
> def r1_x: FooReg<"r1.x">;
> def r1_y: FooReg<"r1.y">;
> def r1_z: FooReg<"r1.z">;
> def r1_w: FooReg<"r1.w">;
> ...
>
> and there are 32 vector registers!
>
>
> i've read Target.rd:
>
> // RegisterGroup - This can be used to define instances of Register which
> // need to specify aliases.
> // List "aliases" specifies which registers are aliased to this one.  This
> // allows the code generator to be careful not to put two values with
> // overlapping live ranges into registers which alias.
> class RegisterGroup<string n, list<Register> aliases> : Register<n> {
>  let Aliases = aliases;
> }
>
>
> but RegisterGroup seems not to be what I need.
>
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-Chris

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