[LLVMdev] How to partition registers into different RegisterClass?

[Tzu-Chien Chiu]

2005/7/26, Chris Lattner <sabre at nondot.org>:
> Tzu-Chien Chiu wrote:
> > The same problem exists when there are two types of costant registers,
> > floating point and integer, and each is declared 'packed' ([4xfloat]
> > and [4xint]). The instruction selector doesn't know which instruction
> > it should produce because the newly defined MVT type 'packed' is
> > always used for all operands (registers), even if it's acutally a
> > [4xfloat] or [4xint].
>
> It might make sense to add two MVT enums: one for packed integers, and one
> for packed floats?

I thought about that too, but what if:
* there are many packed types, 16 and 32-bit floating points, 16 and
32-bit integers, a lot of enums will be needed.
* there number of elements in a packed type could vary.

There could be a more general way to support packed type. The member
fucntion SequentialType::getElementType() returns the type of the
packed elements:

File: include/llvm/Type.h
<code>
  class SequentialType : public CompositeType {
  public:
    inline const Type *getElementType() const { return ContainedTys[0]; }
  };

  class PackedType : public SequentialType {
  public:
    inline unsigned getNumElements() const { return NumElements; }
  };
</code>

If SDOperand can return a "const Type *", the element type of the
packed type can be obtained, and only one enum value 'packed' needed
to be added to MVT::Type. Not only the element type can be available,
but also the number of elements.

-- 
Tzu-Chien Chiu,
3D Graphics Hardware Architect
<URL:http://www.csie.nctu.edu.tw/~jwchiu>