[LLVMdev] Re: LLVM to SUIF-MACH VM binary

[Chris Lattner]

On Tue, 18 Jan 2005, John Cortes wrote:
>> Can you say a little bit about MACH-SUIF?  With a brief google search, I 
>> didn't turn up anything that described the architecture.  Is it a RISC-like 
>> machine with 32-bit instruction words?
>> 
>
> It's another VM representation.  I haven't really gotten to know the nitty 
> gritty of the language so I'm not too confortable with it, but these two 
> links should decribe the project.  It's based on the work from SUIF.  More 
> specifically, we are using MACHINE-SUIF as a backend to SUIF to generate code 
> to an embedded processor.  We want to move away from using the SUIF frontend, 
> but the backend works fine.  Essentially, for right now, I have to convert 
> LLVM IR to SUIFvm IR.
>
> http://www.eecs.harvard.edu/hube/software/nci/suifvm.html
> http://www.eecs.harvard.edu/hube/software/nci/overview.html

Okay, it's a RISCy architecture of sorts.  I don't see any documentation 
on the binary format.  Does it require register allocation?  If not, it 
might be easier to write the target in the style of the C-backend (which 
doesn't use any of the code generator components).  If it does, making use 
of the code generator infrastructure would make sense.

-Chris

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