[LLVMdev] adding new instructions to support "swizzle" and "writemask"
sabre at nondot.org
Wed Apr 20 01:26:17 PDT 2005
On Wed, 20 Apr 2005, Tzu-Chien Chiu wrote:
> I am writing a compiler for a programmable graphics hardware. Each
> registers of the hardware has four channels, namely 'r', 'b', 'g',
> 'a', and each channel is a 32-bit floating point. It's similar to the
> high and low 8-bit of an x86 16-bit general purpose register "AX" can
> be individually referenced as "AH" and "AL". What's different is the
> hardware further "source register swizzle" and "writemask". For
> But implementing swizzle and merge instructions like this seems non-trivial.
> I'd know if anyone knows if there is possible and ealier alternatives?
> Thank you.
I strongly suggest representing these with the LLVM packed type, e.g. as
<4 x double>. This will keep the values together, which you require, and
are first-class SSA values:
Adding the instructions is possible, but for your purposes, I strongly
suggest modelling these as intrinsics, which are much easier to add than
new instructions. For info on adding intrinsics, take a look at:
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