[LLVMdev] TableGen target description file change

[Chris Lattner]

This is just a note for people who have targets that are not in the main
LLVM tree.  I just checked in a patch (contributed by Jason Eckhardt) that
makes the following changes:

1. The 'Register' tablegen class now requires a register name to be
   specified as an argument for the register.  If you had this:

	def FP0 : Register;

   before, change it to:

	def FP0 : Register<"FP0">;

2. The RegisterAliases tablegen class is now gone.  Instead, alias lists
are encoded directly into the Register class, through the use of the
RegisterGroup class.  In the X86 backend, we used to have:

	def AL : Register;
	 ...
	def : RegisterAliases<AL, [AX, EAX]>;

Now you can just define:

	def AL : RegisterGroup<"AL", [AX, EAX]>;

Thanks to Jason for supplying this patch!

-Chris

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