<div dir="ltr"><div>I suspect the issue is the use of OriginalDemandedBits instead of DemandedBits. DemandedBits is set to all ones for multiple uses.</div>
<br clear="all"><div><div dir="ltr" class="gmail_signature" data-smartmail="gmail_signature">~Craig</div></div><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Fri, Aug 18, 2023 at 11:08 AM Thurston Dang via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
Author: Thurston Dang<br>
Date: 2023-08-18T18:08:10Z<br>
New Revision: 29b200906155da393b83232dd31d746ba2ad66a5<br>
<br>
URL: <a href="https://github.com/llvm/llvm-project/commit/29b200906155da393b83232dd31d746ba2ad66a5" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/29b200906155da393b83232dd31d746ba2ad66a5</a><br>
DIFF: <a href="https://github.com/llvm/llvm-project/commit/29b200906155da393b83232dd31d746ba2ad66a5.diff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/29b200906155da393b83232dd31d746ba2ad66a5.diff</a><br>
<br>
LOG: Revert "[DAG] SimplifyDemandedBits - if we're only demanding the signbit, a SMIN/SMAX node can be simplified to a OR/AND node respectively."<br>
<br>
This reverts commit 54d663d5896008c09c938f80357e2a056454bc65, which breaks the test CodeGen/SystemZ/ctpop-01.ll for stage2-ubsan check (see <a href="https://lab.llvm.org/buildbot/#/builders/85/builds/18410" rel="noreferrer" target="_blank">https://lab.llvm.org/buildbot/#/builders/85/builds/18410</a>)<br>
<br>
I manually confirmed that the test had been passing immediately prior to that commit<br>
(BUILDBOT_REVISION=4772c66cfb00d60f8f687930e9dd3aa1b6872228 llvm-zorg/zorg/buildbot/builders/sanitizers/buildbot_bootstrap_ubsan.sh)<br>
<br>
Added: <br>
<br>
<br>
Modified: <br>
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp<br>
llvm/test/CodeGen/X86/smax.ll<br>
llvm/test/CodeGen/X86/smin.ll<br>
<br>
Removed: <br>
<br>
<br>
<br>
################################################################################<br>
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp<br>
index 8bb6724593574c..61b4377337afe2 100644<br>
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp<br>
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp<br>
@@ -1688,22 +1688,6 @@ bool TargetLowering::SimplifyDemandedBits(<br>
Known.Zero.setBitsFrom(1);<br>
break;<br>
}<br>
- case ISD::SMIN: {<br>
- SDValue Op0 = Op.getOperand(0);<br>
- SDValue Op1 = Op.getOperand(1);<br>
- // If we're only wanting the signbit, then we can simplify to OR node.<br>
- if (OriginalDemandedBits.isSignMask())<br>
- return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, VT, Op0, Op1));<br>
- break;<br>
- }<br>
- case ISD::SMAX: {<br>
- SDValue Op0 = Op.getOperand(0);<br>
- SDValue Op1 = Op.getOperand(1);<br>
- // If we're only wanting the signbit, then we can simplify to AND node.<br>
- if (OriginalDemandedBits.isSignMask())<br>
- return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, Op0, Op1));<br>
- break;<br>
- }<br>
case ISD::SHL: {<br>
SDValue Op0 = Op.getOperand(0);<br>
SDValue Op1 = Op.getOperand(1);<br>
<br>
diff --git a/llvm/test/CodeGen/X86/smax.ll b/llvm/test/CodeGen/X86/smax.ll<br>
index 55ee5d50619bd3..d6906b573981ac 100644<br>
--- a/llvm/test/CodeGen/X86/smax.ll<br>
+++ b/llvm/test/CodeGen/X86/smax.ll<br>
@@ -692,7 +692,9 @@ define i64 @test_signbits_i64(i64 %a, i64 %b) nounwind {<br>
; X86-LABEL: test_signbits_i64:<br>
; X86: # %bb.0:<br>
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
-; X86-NEXT: andl {{[0-9]+}}(%esp), %eax<br>
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx<br>
+; X86-NEXT: cmpl %eax, %ecx<br>
+; X86-NEXT: cmovgl %ecx, %eax<br>
; X86-NEXT: movl %eax, %edx<br>
; X86-NEXT: sarl $31, %edx<br>
; X86-NEXT: retl<br>
@@ -707,7 +709,8 @@ define i128 @test_signbits_i128(i128 %a, i128 %b) nounwind {<br>
; X64: # %bb.0:<br>
; X64-NEXT: movq %rcx, %rax<br>
; X64-NEXT: sarq $28, %rax<br>
-; X64-NEXT: andq %rsi, %rax<br>
+; X64-NEXT: cmpq %rax, %rsi<br>
+; X64-NEXT: cmovgq %rsi, %rax<br>
; X64-NEXT: movq %rax, %rdx<br>
; X64-NEXT: sarq $63, %rdx<br>
; X64-NEXT: retq<br>
<br>
diff --git a/llvm/test/CodeGen/X86/smin.ll b/llvm/test/CodeGen/X86/smin.ll<br>
index bb53ec1bceb262..2b059557cdfb50 100644<br>
--- a/llvm/test/CodeGen/X86/smin.ll<br>
+++ b/llvm/test/CodeGen/X86/smin.ll<br>
@@ -693,7 +693,9 @@ define i64 @test_signbits_i64(i64 %a, i64 %b) nounwind {<br>
; X86-LABEL: test_signbits_i64:<br>
; X86: # %bb.0:<br>
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
-; X86-NEXT: orl {{[0-9]+}}(%esp), %eax<br>
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx<br>
+; X86-NEXT: cmpl %eax, %ecx<br>
+; X86-NEXT: cmovll %ecx, %eax<br>
; X86-NEXT: movl %eax, %edx<br>
; X86-NEXT: sarl $31, %edx<br>
; X86-NEXT: retl<br>
@@ -708,7 +710,8 @@ define i128 @test_signbits_i128(i128 %a, i128 %b) nounwind {<br>
; X64: # %bb.0:<br>
; X64-NEXT: movq %rcx, %rax<br>
; X64-NEXT: sarq $28, %rax<br>
-; X64-NEXT: orq %rsi, %rax<br>
+; X64-NEXT: cmpq %rax, %rsi<br>
+; X64-NEXT: cmovlq %rsi, %rax<br>
; X64-NEXT: movq %rax, %rdx<br>
; X64-NEXT: sarq $63, %rdx<br>
; X64-NEXT: retq<br>
<br>
<br>
<br>
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</blockquote></div>