<html><head><meta http-equiv="content-type" content="text/html; charset=utf-8"></head><body style="overflow-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;">Hi Fangrui, this change has broken at least bot <a href="https://green.lab.llvm.org/green/job/clang-stage1-RA/">https://green.lab.llvm.org/green/job/clang-stage1-RA/</a> (started failing in <a href="https://green.lab.llvm.org/green/job/clang-stage1-RA/34684/">https://green.lab.llvm.org/green/job/clang-stage1-RA/34684/</a>). Haven’t checked what other bots might be affected.<div><br></div><div>Can you please take a look at this change and revert/fix it?<br><div><br><blockquote type="cite"><div>On Jun 15, 2023, at 11:26 PM, Fangrui Song via llvm-commits <llvm-commits@lists.llvm.org> wrote:</div><br class="Apple-interchange-newline"><div><div><br>Author: Fangrui Song<br>Date: 2023-06-15T23:26:25-07:00<br>New Revision: 11ebe3d906558d93a607347de472e7718127f409<br><br>URL: https://github.com/llvm/llvm-project/commit/11ebe3d906558d93a607347de472e7718127f409<br>DIFF: https://github.com/llvm/llvm-project/commit/11ebe3d906558d93a607347de472e7718127f409.diff<br><br>LOG: [RISCV] relaxDwarfCallFrameFragment: remove unneeded relocations for relaxation<br><br>If `evaluateAsAbsolute(Value, Layout.getAssembler())` returns true, we<br>know the address delta is a constant and can suppress relocations<br>(usually SET6/SUB6).<br><br>While here, replace two evaluateKnownAbsolute calls (subtle; avoid if possible)<br>with evaluateAsAbsolute.<br><br>Added: <br><br><br>Modified: <br> llvm/lib/MC/MCAssembler.cpp<br> llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp<br> llvm/test/DebugInfo/RISCV/relax-debug-frame.ll<br> llvm/test/MC/ELF/RISCV/gen-dwarf.s<br><br>Removed: <br><br><br><br>################################################################################<br>diff --git a/llvm/lib/MC/MCAssembler.cpp b/llvm/lib/MC/MCAssembler.cpp<br>index f1853bfe2b92f..69ea337e16978 100644<br>--- a/llvm/lib/MC/MCAssembler.cpp<br>+++ b/llvm/lib/MC/MCAssembler.cpp<br>@@ -1110,16 +1110,17 @@ bool MCAssembler::relaxDwarfCallFrameFragment(MCAsmLayout &Layout,<br> return WasRelaxed;<br><br> MCContext &Context = Layout.getAssembler().getContext();<br>- uint64_t OldSize = DF.getContents().size();<br>- int64_t AddrDelta;<br>- bool Abs = DF.getAddrDelta().evaluateKnownAbsolute(AddrDelta, Layout);<br>- assert(Abs && "We created call frame with an invalid expression");<br>- (void) Abs;<br>+ int64_t Value;<br>+ bool Abs = DF.getAddrDelta().evaluateAsAbsolute(Value, Layout);<br>+ assert(Abs && "CFA with invalid expression");<br>+ (void)Abs;<br>+<br> SmallVectorImpl<char> &Data = DF.getContents();<br>+ uint64_t OldSize = Data.size();<br> Data.clear();<br> DF.getFixups().clear();<br><br>- MCDwarfFrameEmitter::encodeAdvanceLoc(Context, AddrDelta, Data);<br>+ MCDwarfFrameEmitter::encodeAdvanceLoc(Context, Value, Data);<br> return OldSize != Data.size();<br> }<br><br><br>diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp<br>index 68dfb6852631c..81542b2697d5f 100644<br>--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp<br>+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp<br>@@ -273,14 +273,15 @@ bool RISCVAsmBackend::relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF,<br> bool RISCVAsmBackend::relaxDwarfCFA(MCDwarfCallFrameFragment &DF,<br> MCAsmLayout &Layout,<br> bool &WasRelaxed) const {<br>-<br> const MCExpr &AddrDelta = DF.getAddrDelta();<br> SmallVectorImpl<char> &Data = DF.getContents();<br> SmallVectorImpl<MCFixup> &Fixups = DF.getFixups();<br> size_t OldSize = Data.size();<br><br> int64_t Value;<br>- bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout);<br>+ if (AddrDelta.evaluateAsAbsolute(Value, Layout.getAssembler()))<br>+ return false;<br>+ bool IsAbsolute = AddrDelta.evaluateAsAbsolute(Value, Layout);<br> assert(IsAbsolute && "CFA with invalid expression");<br> (void)IsAbsolute;<br><br><br>diff --git a/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll b/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll<br>index 557986fa38b56..280da01567a2b 100644<br>--- a/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll<br>+++ b/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll<br>@@ -7,15 +7,29 @@<br> ; RELAX-NEXT: 0x1C R_RISCV_32_PCREL - 0x0<br> ; RELAX-NEXT: 0x20 R_RISCV_ADD32 - 0x0<br> ; RELAX-NEXT: 0x20 R_RISCV_SUB32 - 0x0<br>-; RELAX-NOT: }<br>-; RELAX: 0x39 R_RISCV_SET6 - 0x0<br>-; RELAX-NEXT: 0x39 R_RISCV_SUB6 - 0x0<br>-;<br>+; RELAX-NEXT: 0x30 R_RISCV_32_PCREL - 0x0<br>+; RELAX-NEXT: 0x34 R_RISCV_ADD32 - 0x0<br>+; RELAX-NEXT: 0x34 R_RISCV_SUB32 - 0x0<br>+; RELAX-NEXT: 0x44 R_RISCV_32_PCREL - 0x0<br>+; RELAX-NEXT: 0x48 R_RISCV_ADD32 - 0x0<br>+; RELAX-NEXT: 0x48 R_RISCV_SUB32 - 0x0<br>+; RELAX-NEXT: }<br>+<br> ; RELAX-DWARFDUMP-NOT: error: failed to compute relocation<br>-; RELAX-DWARFDUMP: CIE<br>-; RELAX-DWARFDUMP: DW_CFA_advance_loc<br>-; RELAX-DWARFDUMP: DW_CFA_def_cfa_offset<br>-; RELAX-DWARFDUMP: DW_CFA_offset<br>+; RELAX-DWARFDUMP: FDE<br>+; RELAX-DWARFDUMP-NEXT: Format:<br>+; RELAX-DWARFDUMP: DW_CFA_advance_loc: 4<br>+; RELAX-DWARFDUMP-NEXT: DW_CFA_def_cfa_offset: +16<br>+; RELAX-DWARFDUMP-EMPTY:<br>+<br>+; RELAX-DWARFDUMP: FDE<br>+; RELAX-DWARFDUMP: Format:<br>+; RELAX-DWARFDUMP-NEXT: DW_CFA_advance_loc: 4<br>+; RELAX-DWARFDUMP-NEXT: DW_CFA_def_cfa_offset: +16<br>+; RELAX-DWARFDUMP-NEXT: DW_CFA_advance_loc: 4<br>+; RELAX-DWARFDUMP-NEXT: DW_CFA_offset: X1 -4<br>+; RELAX-DWARFDUMP-NEXT: DW_CFA_nop<br>+; RELAX-DWARFDUMP-EMPTY:<br> source_filename = "frame.c"<br><br> ; Function Attrs: noinline nounwind optnone<br><br>diff --git a/llvm/test/MC/ELF/RISCV/gen-dwarf.s b/llvm/test/MC/ELF/RISCV/gen-dwarf.s<br>index a9e9d2c730bbb..c0c8cae61c72b 100644<br>--- a/llvm/test/MC/ELF/RISCV/gen-dwarf.s<br>+++ b/llvm/test/MC/ELF/RISCV/gen-dwarf.s<br>@@ -45,8 +45,6 @@<br> # RELOC-NEXT: 0x20 R_RISCV_SUB32 - 0x0<br> # RELOC-NEXT: 0x25 R_RISCV_SET6 - 0x0<br> # RELOC-NEXT: 0x25 R_RISCV_SUB6 - 0x0<br>-# RELOC-NEXT: 0x28 R_RISCV_SET6 - 0x0<br>-# RELOC-NEXT: 0x28 R_RISCV_SUB6 - 0x0<br> # RELOC-NEXT: 0x34 R_RISCV_32_PCREL - 0x0<br> # RELOC-NEXT: 0x38 R_RISCV_ADD32 - 0x0<br> # RELOC-NEXT: 0x38 R_RISCV_SUB32 - 0x0<br><br><br><br>_______________________________________________<br>llvm-commits mailing list<br>llvm-commits@lists.llvm.org<br>https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits<br></div></div></blockquote></div><br></div></body></html>