<div dir="ltr">How much impact does this save on isel table size? I mainly suggested it on rotate/shift because we had the function anyway. Now we're introducing new functions that have their own cost. Is this the right tradeoff?<div><br clear="all"><div><div dir="ltr" class="gmail_signature" data-smartmail="gmail_signature">~Craig</div></div><br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, May 18, 2023 at 7:34 PM Shengchen Kan via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
Author: Shengchen Kan<br>
Date: 2023-05-19T10:33:52+08:00<br>
New Revision: 2ef8ae134828876ab3ebda4a81bb2df7b095d030<br>
<br>
URL: <a href="https://github.com/llvm/llvm-project/commit/2ef8ae134828876ab3ebda4a81bb2df7b095d030" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/2ef8ae134828876ab3ebda4a81bb2df7b095d030</a><br>
DIFF: <a href="https://github.com/llvm/llvm-project/commit/2ef8ae134828876ab3ebda4a81bb2df7b095d030.diff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/2ef8ae134828876ab3ebda4a81bb2df7b095d030.diff</a><br>
<br>
LOG: [X86] Remove patterns for ADC/SBB with immediate 8 and optimize during MC lowering, NFCI<br>
<br>
This is follow-up of D150107.<br>
<br>
Added: <br>
<br>
<br>
Modified: <br>
llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp<br>
llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.h<br>
llvm/lib/Target/X86/X86InstrArithmetic.td<br>
llvm/lib/Target/X86/X86InstrInfo.cpp<br>
llvm/lib/Target/X86/X86MCInstLower.cpp<br>
<br>
Removed: <br>
<br>
<br>
<br>
################################################################################<br>
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp<br>
index 69f65841d7b57..5299583714466 100644<br>
--- a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp<br>
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp<br>
@@ -424,3 +424,27 @@ bool X86::optimizeToFixedRegisterForm(MCInst &MI) {<br>
MI.addOperand(Saved);<br>
return true;<br>
}<br>
+<br>
+bool X86::optimizeToShortImmediateForm(MCInst &MI) {<br>
+ unsigned NewOpc;<br>
+ switch (MI.getOpcode()) {<br>
+ default:<br>
+ return false;<br>
+ FROM_TO(ADC16mi, ADC16mi8)<br>
+ FROM_TO(ADC16ri, ADC16ri8)<br>
+ FROM_TO(ADC32mi, ADC32mi8)<br>
+ FROM_TO(ADC32ri, ADC32ri8)<br>
+ FROM_TO(ADC64mi32, ADC64mi8)<br>
+ FROM_TO(ADC64ri32, ADC64ri8)<br>
+ FROM_TO(SBB16mi, SBB16mi8)<br>
+ FROM_TO(SBB16ri, SBB16ri8)<br>
+ FROM_TO(SBB32mi, SBB32mi8)<br>
+ FROM_TO(SBB32ri, SBB32ri8)<br>
+ FROM_TO(SBB64mi32, SBB64mi8)<br>
+ FROM_TO(SBB64ri32, SBB64ri8)<br>
+ }<br>
+ if (!isInt<8>(MI.getOperand(MI.getNumOperands() - 1).getImm()))<br>
+ return false;<br>
+ MI.setOpcode(NewOpc);<br>
+ return true;<br>
+}<br>
<br>
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.h b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.h<br>
index 7d0c31751e84a..169283c5421ba 100644<br>
--- a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.h<br>
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.h<br>
@@ -23,6 +23,7 @@ bool optimizeMOVSX(MCInst &MI);<br>
bool optimizeINCDEC(MCInst &MI, bool In64BitMode);<br>
bool optimizeMOV(MCInst &MI, bool In64BitMode);<br>
bool optimizeToFixedRegisterForm(MCInst &MI);<br>
+bool optimizeToShortImmediateForm(MCInst &MI);<br>
} // namespace X86<br>
} // namespace llvm<br>
#endif<br>
<br>
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td<br>
index c4e4eb333882f..54cd2836724e6 100644<br>
--- a/llvm/lib/Target/X86/X86InstrArithmetic.td<br>
+++ b/llvm/lib/Target/X86/X86InstrArithmetic.td<br>
@@ -251,14 +251,9 @@ class BinOpRI8_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,<br>
[(set typeinfo.RegClass:$dst, EFLAGS,<br>
(opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;<br>
<br>
-// BinOpRI8_RFF - Binary instructions with inputs "reg, imm8", where the pattern<br>
-// has both a regclass and EFLAGS as a result, and has EFLAGS as input.<br>
-class BinOpRI8_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,<br>
- SDPatternOperator opnode, Format f><br>
- : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst), WriteADC,<br>
- [(set typeinfo.RegClass:$dst, EFLAGS,<br>
- (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2,<br>
- EFLAGS))]>;<br>
+// BinOpRI8_RFF - Binary instructions with inputs "reg, imm8".<br>
+class BinOpRI8_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, Format f><br>
+ : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst), WriteADC, []>;<br>
<br>
// BinOpMR - Binary instructions with inputs "[mem], reg".<br>
class BinOpMR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,<br>
@@ -362,15 +357,9 @@ class BinOpMI8_RMW<string mnemonic, X86TypeInfo typeinfo,<br>
(implicit EFLAGS)]>,<br>
Sched<[WriteALURMW]>;<br>
<br>
-// BinOpMI8_RMW_FF - Binary instructions with inputs "[mem], imm8", where the<br>
-// pattern sets EFLAGS and implicitly uses EFLAGS.<br>
-class BinOpMI8_RMW_FF<string mnemonic, X86TypeInfo typeinfo,<br>
- SDPatternOperator opnode, Format f><br>
- : BinOpMI8<mnemonic, typeinfo, f,<br>
- [(store (opnode (load addr:$dst),<br>
- typeinfo.Imm8Operator:$src, EFLAGS), addr:$dst),<br>
- (implicit EFLAGS)]>,<br>
- Sched<[WriteADCRMW]>;<br>
+// BinOpMI8_RMW_FF - Binary instructions with inputs "[mem], imm8".<br>
+class BinOpMI8_RMW_FF<string mnemonic, X86TypeInfo typeinfo, Format f><br>
+ : BinOpMI8<mnemonic, typeinfo, f, []>, Sched<[WriteADCRMW]>;<br>
<br>
// BinOpMI8_F - Binary instructions with inputs "[mem], imm8", where the pattern<br>
// has EFLAGS as a result.<br>
@@ -979,9 +968,9 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,<br>
let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {<br>
// NOTE: These are order specific, we want the ri8 forms to be listed<br>
// first so that they are slightly preferred to the ri forms.<br>
- def NAME#16ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi16, opnode, RegMRM>;<br>
- def NAME#32ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi32, opnode, RegMRM>;<br>
- def NAME#64ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi64, opnode, RegMRM>;<br>
+ def NAME#16ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi16, RegMRM>;<br>
+ def NAME#32ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi32, RegMRM>;<br>
+ def NAME#64ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi64, RegMRM>;<br>
<br>
def NAME#16ri : BinOpRI_RFF<0x80, mnemonic, Xi16, opnode, RegMRM>;<br>
def NAME#32ri : BinOpRI_RFF<0x80, mnemonic, Xi32, opnode, RegMRM>;<br>
@@ -996,10 +985,10 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,<br>
<br>
// NOTE: These are order specific, we want the mi8 forms to be listed<br>
// first so that they are slightly preferred to the mi forms.<br>
- def NAME#16mi8 : BinOpMI8_RMW_FF<mnemonic, Xi16, opnode, MemMRM>;<br>
- def NAME#32mi8 : BinOpMI8_RMW_FF<mnemonic, Xi32, opnode, MemMRM>;<br>
+ def NAME#16mi8 : BinOpMI8_RMW_FF<mnemonic, Xi16, MemMRM>;<br>
+ def NAME#32mi8 : BinOpMI8_RMW_FF<mnemonic, Xi32, MemMRM>;<br>
let Predicates = [In64BitMode] in<br>
- def NAME#64mi8 : BinOpMI8_RMW_FF<mnemonic, Xi64, opnode, MemMRM>;<br>
+ def NAME#64mi8 : BinOpMI8_RMW_FF<mnemonic, Xi64, MemMRM>;<br>
<br>
def NAME#8mi : BinOpMI_RMW_FF<0x80, mnemonic, Xi8 , opnode, MemMRM>;<br>
def NAME#16mi : BinOpMI_RMW_FF<0x80, mnemonic, Xi16, opnode, MemMRM>;<br>
@@ -1012,9 +1001,9 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,<br>
let Predicates = [Not64BitMode], isCodeGenOnly = 1, ForceDisassemble = 1,<br>
hasSideEffects = 0 in {<br>
let Constraints = "$src1 = $dst" in<br>
- def NAME#8ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi8, null_frag, RegMRM>;<br>
+ def NAME#8ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi8, RegMRM>;<br>
let mayLoad = 1, mayStore = 1 in<br>
- def NAME#8mi8 : BinOpMI8_RMW_FF<mnemonic, Xi8, null_frag, MemMRM>;<br>
+ def NAME#8mi8 : BinOpMI8_RMW_FF<mnemonic, Xi8, MemMRM>;<br>
}<br>
} // Uses = [EFLAGS], Defs = [EFLAGS]<br>
<br>
<br>
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp<br>
index 1f66035fce76d..48be6ff35d3f3 100644<br>
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp<br>
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp<br>
@@ -4245,13 +4245,11 @@ inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag,<br>
case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:<br>
case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:<br>
case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:<br>
- case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:<br>
- case X86::ADC32ri8: case X86::ADC16ri: case X86::ADC16ri8:<br>
+ case X86::ADC64ri32: case X86::ADC32ri: case X86::ADC16ri:<br>
case X86::ADC8ri: case X86::ADC64rr: case X86::ADC32rr:<br>
case X86::ADC16rr: case X86::ADC8rr: case X86::ADC64rm:<br>
case X86::ADC32rm: case X86::ADC16rm: case X86::ADC8rm:<br>
- case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:<br>
- case X86::SBB32ri8: case X86::SBB16ri: case X86::SBB16ri8:<br>
+ case X86::SBB64ri32: case X86::SBB32ri: case X86::SBB16ri:<br>
case X86::SBB8ri: case X86::SBB64rr: case X86::SBB32rr:<br>
case X86::SBB16rr: case X86::SBB8rr: case X86::SBB64rm:<br>
case X86::SBB32rm: case X86::SBB16rm: case X86::SBB8rm:<br>
<br>
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp<br>
index 9194f4485eb92..c4a40bf817037 100644<br>
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp<br>
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp<br>
@@ -405,7 +405,8 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {<br>
X86::optimizeVPCMPWithImmediateOneOrSix(OutMI) ||<br>
X86::optimizeMOVSX(OutMI) || X86::optimizeINCDEC(OutMI, In64BitMode) ||<br>
X86::optimizeMOV(OutMI, In64BitMode) ||<br>
- X86::optimizeToFixedRegisterForm(OutMI))<br>
+ X86::optimizeToFixedRegisterForm(OutMI) ||<br>
+ X86::optimizeToShortImmediateForm(OutMI))<br>
return;<br>
<br>
// Handle a few special cases to eliminate operand modifiers.<br>
<br>
<br>
<br>
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</blockquote></div>