<div dir="ltr">Please include the reason for reverting a patch.<div><br clear="all"><div><div dir="ltr" class="gmail_signature" data-smartmail="gmail_signature">~Craig</div></div><br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Jun 30, 2022 at 5:59 PM Xiang1 Zhang via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
Author: Xiang1 Zhang<br>
Date: 2022-07-01T08:59:04+08:00<br>
New Revision: 64f44a90efb70dd5853e870a6f2c38e2f47ff890<br>
<br>
URL: <a href="https://github.com/llvm/llvm-project/commit/64f44a90efb70dd5853e870a6f2c38e2f47ff890" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/64f44a90efb70dd5853e870a6f2c38e2f47ff890</a><br>
DIFF: <a href="https://github.com/llvm/llvm-project/commit/64f44a90efb70dd5853e870a6f2c38e2f47ff890.diff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/64f44a90efb70dd5853e870a6f2c38e2f47ff890.diff</a><br>
<br>
LOG: Revert "[ISel] Match all bits when merge undef(s) for DAG combine"<br>
<br>
This reverts commit 5fe5aa284efed1ee1492e1f266351b35f0a8bb69.<br>
<br>
Added: <br>
<br>
<br>
Modified: <br>
llvm/include/llvm/ADT/APInt.h<br>
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp<br>
llvm/lib/Support/APInt.cpp<br>
llvm/test/CodeGen/X86/fshl-splat-undef.ll<br>
llvm/unittests/ADT/APIntTest.cpp<br>
<br>
Removed: <br>
<br>
<br>
<br>
################################################################################<br>
diff --git a/llvm/include/llvm/ADT/APInt.h b/llvm/include/llvm/ADT/APInt.h<br>
index 4155cb260a2a5..5d8ae2794ce90 100644<br>
--- a/llvm/include/llvm/ADT/APInt.h<br>
+++ b/llvm/include/llvm/ADT/APInt.h<br>
@@ -2239,16 +2239,12 @@ Optional<unsigned> GetMostSignificantDifferentBit(const APInt &A,<br>
/// Splat/Merge neighboring bits to widen/narrow the bitmask represented<br>
/// by \param A to \param NewBitWidth bits.<br>
///<br>
-/// MatchAnyBits: (Default)<br>
/// e.g. ScaleBitMask(0b0101, 8) -> 0b00110011<br>
/// e.g. ScaleBitMask(0b00011011, 4) -> 0b0111<br>
-///<br>
-/// MatchAllBits:<br>
-/// e.g. ScaleBitMask(0b0101, 8) -> 0b00110011<br>
-/// e.g. ScaleBitMask(0b00011011, 4) -> 0b0001<br>
/// A.getBitwidth() or NewBitWidth must be a whole multiples of the other.<br>
-APInt ScaleBitMask(const APInt &A, unsigned NewBitWidth,<br>
- bool MatchAllBits = false);<br>
+///<br>
+/// TODO: Do we need a mode where all bits must be set when merging down?<br>
+APInt ScaleBitMask(const APInt &A, unsigned NewBitWidth);<br>
} // namespace APIntOps<br>
<br>
// See friend declaration above. This additional declaration is required in<br>
<br>
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp<br>
index b3b8756ae9ba6..bc1011b69c9df 100644<br>
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp<br>
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp<br>
@@ -2712,16 +2712,7 @@ bool SelectionDAG::isSplatValue(SDValue V, const APInt &DemandedElts,<br>
SubDemandedElts &= ScaledDemandedElts;<br>
if (!isSplatValue(Src, SubDemandedElts, SubUndefElts, Depth + 1))<br>
return false;<br>
-<br>
- // Here we can't do "MatchAnyBits" operation merge for undef bits.<br>
- // Because some operation only use part value of the source.<br>
- // Take llvm.fshl.* for example:<br>
- // t1: v4i32 = Constant:i32<12>, undef:i32, Constant:i32<12>, undef:i32<br>
- // t2: v2i64 = bitcast t1<br>
- // t5: v2i64 = fshl t3, t4, t2<br>
- // We can not convert t2 to {i64 undef, i64 undef}<br>
- UndefElts |= APIntOps::ScaleBitMask(SubUndefElts, NumElts,<br>
- /*MatchAllBits=*/true);<br>
+ UndefElts |= APIntOps::ScaleBitMask(SubUndefElts, NumElts);<br>
}<br>
return true;<br>
}<br>
<br>
diff --git a/llvm/lib/Support/APInt.cpp b/llvm/lib/Support/APInt.cpp<br>
index f74178b1ba4e1..acc68fe0be957 100644<br>
--- a/llvm/lib/Support/APInt.cpp<br>
+++ b/llvm/lib/Support/APInt.cpp<br>
@@ -2968,8 +2968,7 @@ llvm::APIntOps::GetMostSignificantDifferentBit(const APInt &A, const APInt &B) {<br>
return A.getBitWidth() - ((A ^ B).countLeadingZeros() + 1);<br>
}<br>
<br>
-APInt llvm::APIntOps::ScaleBitMask(const APInt &A, unsigned NewBitWidth,<br>
- bool MatchAllBits) {<br>
+APInt llvm::APIntOps::ScaleBitMask(const APInt &A, unsigned NewBitWidth) {<br>
unsigned OldBitWidth = A.getBitWidth();<br>
assert((((OldBitWidth % NewBitWidth) == 0) ||<br>
((NewBitWidth % OldBitWidth) == 0)) &&<br>
@@ -2993,16 +2992,11 @@ APInt llvm::APIntOps::ScaleBitMask(const APInt &A, unsigned NewBitWidth,<br>
if (A[i])<br>
NewA.setBits(i * Scale, (i + 1) * Scale);<br>
} else {<br>
+ // Merge bits - if any old bit is set, then set scale equivalent new bit.<br>
unsigned Scale = OldBitWidth / NewBitWidth;<br>
- for (unsigned i = 0; i != NewBitWidth; ++i) {<br>
- if (MatchAllBits) {<br>
- if (A.extractBits(Scale, i * Scale).isAllOnes())<br>
- NewA.setBit(i);<br>
- } else {<br>
- if (!A.extractBits(Scale, i * Scale).isZero())<br>
- NewA.setBit(i);<br>
- }<br>
- }<br>
+ for (unsigned i = 0; i != NewBitWidth; ++i)<br>
+ if (!A.extractBits(Scale, i * Scale).isZero())<br>
+ NewA.setBit(i);<br>
}<br>
<br>
return NewA;<br>
<br>
diff --git a/llvm/test/CodeGen/X86/fshl-splat-undef.ll b/llvm/test/CodeGen/X86/fshl-splat-undef.ll<br>
index 365c3e32e0a0a..a0afbdc0cd5f2 100644<br>
--- a/llvm/test/CodeGen/X86/fshl-splat-undef.ll<br>
+++ b/llvm/test/CodeGen/X86/fshl-splat-undef.ll<br>
@@ -20,14 +20,8 @@<br>
define void @test_fshl(<8 x i64> %lo, <8 x i64> %hi, <8 x i64>* %arr) {<br>
; CHECK-LABEL: test_fshl:<br>
; CHECK: # %bb.0: # %entry<br>
-; CHECK-NEXT: movl $63, %eax<br>
-; CHECK-NEXT: vmovd %eax, %xmm2<br>
-; CHECK-NEXT: movl $12, %eax<br>
-; CHECK-NEXT: vmovd %eax, %xmm3<br>
-; CHECK-NEXT: vpand %xmm2, %xmm3, %xmm2<br>
-; CHECK-NEXT: vpsllq %xmm2, %zmm1, %zmm1<br>
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
-; CHECK-NEXT: vpsrlq $52, %zmm0, %zmm0<br>
+; CHECK-NEXT: vpsrlq $1, %zmm0, %zmm0<br>
; CHECK-NEXT: vpternlogq $168, {{\.?LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm0<br>
; CHECK-NEXT: vmovdqa64 %zmm0, (%eax)<br>
; CHECK-NEXT: vzeroupper<br>
<br>
diff --git a/llvm/unittests/ADT/APIntTest.cpp b/llvm/unittests/ADT/APIntTest.cpp<br>
index 0af294c609698..e92754cc2ccd1 100644<br>
--- a/llvm/unittests/ADT/APIntTest.cpp<br>
+++ b/llvm/unittests/ADT/APIntTest.cpp<br>
@@ -3115,15 +3115,6 @@ TEST(APIntTest, ScaleBitMask) {<br>
APInt::getAllOnes(256));<br>
EXPECT_EQ(APIntOps::ScaleBitMask(APInt::getOneBitSet(4096, 32), 256),<br>
APInt::getOneBitSet(256, 2));<br>
-<br>
- EXPECT_EQ(APIntOps::ScaleBitMask(APInt(2, 0x00), 8, true), APInt(8, 0x00));<br>
- EXPECT_EQ(APIntOps::ScaleBitMask(APInt(2, 0x01), 8, true), APInt(8, 0x0F));<br>
- EXPECT_EQ(APIntOps::ScaleBitMask(APInt(2, 0x02), 8, true), APInt(8, 0xF0));<br>
- EXPECT_EQ(APIntOps::ScaleBitMask(APInt(2, 0x03), 8, true), APInt(8, 0xFF));<br>
-<br>
- EXPECT_EQ(APIntOps::ScaleBitMask(APInt(8, 0x00), 4, true), APInt(4, 0x00));<br>
- EXPECT_EQ(APIntOps::ScaleBitMask(APInt(8, 0xFF), 4, true), APInt(4, 0x0F));<br>
- EXPECT_EQ(APIntOps::ScaleBitMask(APInt(8, 0xE4), 4, true), APInt(4, 0x08));<br>
}<br>
<br>
} // end anonymous namespace<br>
<br>
<br>
<br>
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</blockquote></div>