<div dir="ltr"><div>+1 to revert; the failure example seems viable. Hopefully, there's some other way to avoid the problem in D109368.</div><div>The existing folding in the builder goes back a very long time and IIRC was there to prevent some inefficiency that was noticeable in overall compile-time. If we can't see that difference currently, we should remove those folds. We don't want to recreate instsimplify in the IRBuilder.<br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Wed, Oct 27, 2021 at 2:55 PM Nikita Popov <<a href="mailto:nikita.ppv@gmail.com">nikita.ppv@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr"><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Wed, Oct 27, 2021 at 8:35 PM Roman Lebedev via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
Author: Roman Lebedev<br>
Date: 2021-10-27T21:34:38+03:00<br>
New Revision: cb90e5356ac1594e95fed8e208d6e0e9b6a87db1<br>
<br>
URL: <a href="https://github.com/llvm/llvm-project/commit/cb90e5356ac1594e95fed8e208d6e0e9b6a87db1" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/cb90e5356ac1594e95fed8e208d6e0e9b6a87db1</a><br>
DIFF: <a href="https://github.com/llvm/llvm-project/commit/cb90e5356ac1594e95fed8e208d6e0e9b6a87db1.diff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/cb90e5356ac1594e95fed8e208d6e0e9b6a87db1.diff</a><br>
<br>
LOG: [IR] `IRBuilderBase::CreateAdd()`: short-circuit `x + 0` --> `x`<br>
<br>
There's precedent for that in `CreateOr()`/`CreateAnd()`.<br>
<br>
The motivation here is to avoid bloating the run-time check's IR<br>
in `SCEVExpander::generateOverflowCheck()`.<br>
<br>
Refs. <a href="https://reviews.llvm.org/D109368#3089809" rel="noreferrer" target="_blank">https://reviews.llvm.org/D109368#3089809</a></blockquote><div><br></div><div>I'm not sure that it is appropriate to introduce these kinds of folds in IRBuilder. One thing in particular this breaks in a really dangerous way is the semi-common pattern of doing something like this:</div><div><br></div><div>Value *X = Builder.CreateAdd(A, B);</div><div>if (auto *BO = dyn_cast<BinaryOperator>(X))</div><div> BO->setHasNoUnsignedWrap(NUW);<br></div><div><br></div><div>This can now fail in a very subtle way, because CreateAdd might fold the result to either A or B, which might be a BinaryOperator, and then the flag ends up getting set on the wrong instruction. And it will only happen in degenerate cases (one operand zero and the other a binary operator), so you're unlikely to catch it in simple tests.<br></div><div><br></div><div>Here is an example of this kind of usage: <a href="https://github.com/llvm/llvm-project/blob/cb90e5356ac1594e95fed8e208d6e0e9b6a87db1/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp#L1276-L1280" target="_blank">https://github.com/llvm/llvm-project/blob/cb90e5356ac1594e95fed8e208d6e0e9b6a87db1/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp#L1276-L1280</a> From a very cursory look, I think the described issue may affect this usage depending on worklist order (i.e. if a 0 << shamt hasn't been folded yet).<br></div><div><br></div><div>I realize that what you're doing here is not entirely new, but it was previously limited to just CreateAnd/CreateOr, which at least don't take attributes or metadata, so it was less problematic in practice. Arguably that fold shouldn't exist either though. I think it would be good to revert and go through a review on these changes, as they change IRBuilder semantics/guarantees in a significant way.<br></div><div><br></div><div>Regards,</div><div>Nikita<br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Added: <br>
<br>
<br>
Modified: <br>
clang/test/CodeGen/catch-nullptr-and-nonzero-offset.c<br>
clang/test/CodeGen/complex-convert.c<br>
clang/test/CodeGen/matrix-type-operators.c<br>
clang/test/CodeGen/volatile-1.c<br>
clang/test/CodeGenCXX/microsoft-abi-virtual-inheritance.cpp<br>
clang/test/CodeGenCXX/virtual-base-cast.cpp<br>
clang/test/CodeGenCXX/volatile-1.cpp<br>
clang/test/CodeGenOpenCLCXX/addrspace-operators.clcpp<br>
llvm/include/llvm/IR/IRBuilder.h<br>
llvm/test/Instrumentation/AddressSanitizer/fake-stack.ll<br>
llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime-be.ll<br>
llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime.ll<br>
llvm/test/Instrumentation/HWAddressSanitizer/basic.ll<br>
llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll<br>
llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll<br>
llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll<br>
llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll<br>
llvm/test/Transforms/LoopDistribute/scev-inserted-runtime-check.ll<br>
llvm/test/Transforms/LoopIdiom/X86/arithmetic-right-shift-until-zero.ll<br>
llvm/test/Transforms/LoopIdiom/X86/left-shift-until-zero.ll<br>
llvm/test/Transforms/LoopIdiom/X86/logical-right-shift-until-zero.ll<br>
llvm/test/Transforms/LoopVectorize/AArch64/induction-trunc.ll<br>
llvm/test/Transforms/LoopVectorize/AArch64/scalarize-store-with-predication.ll<br>
llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll<br>
llvm/test/Transforms/LoopVectorize/ARM/tail-folding-scalar-epilogue-fallback.ll<br>
llvm/test/Transforms/LoopVectorize/X86/cost-model-assert.ll<br>
llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll<br>
llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll<br>
llvm/test/Transforms/LoopVectorize/if-pred-stores.ll<br>
llvm/test/Transforms/LoopVectorize/pointer-induction.ll<br>
llvm/test/Transforms/LoopVectorize/pr30654-phiscev-sext-trunc.ll<br>
llvm/test/Transforms/LoopVectorize/pr45679-fold-tail-by-masking.ll<br>
llvm/test/Transforms/LoopVectorize/runtime-check-small-clamped-bounds.ll<br>
llvm/test/Transforms/LoopVectorize/select-cmp-predicated.ll<br>
llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll<br>
llvm/test/Transforms/LoopVectorize/unroll_nonlatch.ll<br>
llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll<br>
llvm/test/Transforms/LoopVersioning/wrapping-pointer-versioning.ll<br>
llvm/unittests/IR/PatternMatch.cpp<br>
<br>
Removed: <br>
<br>
<br>
<br>
################################################################################<br>
diff --git a/clang/test/CodeGen/catch-nullptr-and-nonzero-offset.c b/clang/test/CodeGen/catch-nullptr-and-nonzero-offset.c<br>
index 22acc1e865329..08eea57dcba80 100644<br>
--- a/clang/test/CodeGen/catch-nullptr-and-nonzero-offset.c<br>
+++ b/clang/test/CodeGen/catch-nullptr-and-nonzero-offset.c<br>
@@ -83,16 +83,15 @@ char *var_zero(char *base) {<br>
// CHECK-NEXT: %[[BASE_RELOADED:.*]] = load i8*, i8** %[[BASE_ADDR]], align 8<br>
// CHECK-NEXT: %[[ADD_PTR:.*]] = getelementptr inbounds i8, i8* %[[BASE_RELOADED]], i64 0<br>
// CHECK-SANITIZE-C-NEXT: %[[BASE_RELOADED_INT:.*]] = ptrtoint i8* %[[BASE_RELOADED]] to i64, !nosanitize<br>
- // CHECK-SANITIZE-C-NEXT: %[[COMPUTED_GEP:.*]] = add i64 %[[BASE_RELOADED_INT]], 0, !nosanitize<br>
// CHECK-SANITIZE-C-NEXT: %[[BASE_IS_NOT_NULLPTR:.*]] = icmp ne i8* %[[BASE_RELOADED]], null, !nosanitize<br>
- // CHECK-SANITIZE-C-NEXT: %[[COMPUTED_GEP_IS_NOT_NULL:.*]] = icmp ne i64 %[[COMPUTED_GEP]], 0, !nosanitize<br>
+ // CHECK-SANITIZE-C-NEXT: %[[COMPUTED_GEP_IS_NOT_NULL:.*]] = icmp ne i64 %[[BASE_RELOADED_INT]], 0, !nosanitize<br>
// CHECK-SANITIZE-C-NEXT: %[[BOTH_POINTERS_ARE_NULL_OR_BOTH_ARE_NONNULL:.*]] = and i1 %[[BASE_IS_NOT_NULLPTR]], %[[COMPUTED_GEP_IS_NOT_NULL]], !nosanitize<br>
- // CHECK-SANITIZE-C-NEXT: %[[COMPUTED_GEP_IS_UGE_BASE:.*]] = icmp uge i64 %[[COMPUTED_GEP]], %[[BASE_RELOADED_INT]], !nosanitize<br>
+ // CHECK-SANITIZE-C-NEXT: %[[COMPUTED_GEP_IS_UGE_BASE:.*]] = icmp uge i64 %[[BASE_RELOADED_INT]], %[[BASE_RELOADED_INT]], !nosanitize<br>
// CHECK-SANITIZE-C-NEXT: %[[GEP_IS_OKAY:.*]] = and i1 %[[BOTH_POINTERS_ARE_NULL_OR_BOTH_ARE_NONNULL]], %[[COMPUTED_GEP_IS_UGE_BASE]], !nosanitize<br>
// CHECK-SANITIZE-C-NEXT: br i1 %[[GEP_IS_OKAY]], label %[[CONT:.*]], label %[[HANDLER_POINTER_OVERFLOW:[^,]+]],{{.*}} !nosanitize<br>
// CHECK-SANITIZE-C: [[HANDLER_POINTER_OVERFLOW]]:<br>
- // CHECK-SANITIZE-NORECOVER-C-NEXT: call void @__ubsan_handle_pointer_overflow_abort(i8* bitcast ({ {{{.*}}} }* @[[LINE_200]] to i8*), i64 %[[BASE_RELOADED_INT]], i64 %[[COMPUTED_GEP]])<br>
- // CHECK-SANITIZE-RECOVER-C-NEXT: call void @__ubsan_handle_pointer_overflow(i8* bitcast ({ {{{.*}}} }* @[[LINE_200]] to i8*), i64 %[[BASE_RELOADED_INT]], i64 %[[COMPUTED_GEP]])<br>
+ // CHECK-SANITIZE-NORECOVER-C-NEXT: call void @__ubsan_handle_pointer_overflow_abort(i8* bitcast ({ {{{.*}}} }* @[[LINE_200]] to i8*), i64 %[[BASE_RELOADED_INT]], i64 %[[BASE_RELOADED_INT]])<br>
+ // CHECK-SANITIZE-RECOVER-C-NEXT: call void @__ubsan_handle_pointer_overflow(i8* bitcast ({ {{{.*}}} }* @[[LINE_200]] to i8*), i64 %[[BASE_RELOADED_INT]], i64 %[[BASE_RELOADED_INT]])<br>
// CHECK-SANITIZE-TRAP-C-NEXT: call void @llvm.ubsantrap(i8 19){{.*}}, !nosanitize<br>
// CHECK-SANITIZE-UNREACHABLE-C-NEXT: unreachable, !nosanitize<br>
// CHECK-SANITIZE-C: [[CONT]]:<br>
@@ -170,18 +169,17 @@ char *nullptr_var(unsigned long offset) {<br>
// CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET_AGGREGATE:.*]] = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 1, i64 %[[OFFSET_RELOADED]]), !nosanitize<br>
// CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET_OVERFLOWED:.*]] = extractvalue { i64, i1 } %[[COMPUTED_OFFSET_AGGREGATE]], 1, !nosanitize<br>
// CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET:.*]] = extractvalue { i64, i1 } %[[COMPUTED_OFFSET_AGGREGATE]], 0, !nosanitize<br>
- // CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP:.*]] = add i64 %[[COMPUTED_OFFSET]], 0, !nosanitize<br>
- // CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP_IS_NOT_NULL:.*]] = icmp ne i64 %[[COMPUTED_GEP]], 0, !nosanitize<br>
- // CHECK-SANITIZE-CPP-NEXT: %[[BOTH_POINTERS_ARE_NULL_OR_BOTH_ARE_NONNULL:.*]] = icmp eq i1 false, %[[COMPUTED_GEP_IS_NOT_NULL]], !nosanitize<br>
+ // CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET_IS_NOT_NULL:.*]] = icmp ne i64 %[[COMPUTED_OFFSET]], 0, !nosanitize<br>
+ // CHECK-SANITIZE-CPP-NEXT: %[[BOTH_POINTERS_ARE_NULL_OR_BOTH_ARE_NONNULL:.*]] = icmp eq i1 false, %[[COMPUTED_OFFSET_IS_NOT_NULL]], !nosanitize<br>
// CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET_DID_NOT_OVERFLOW:.*]] = xor i1 %[[COMPUTED_OFFSET_OVERFLOWED]], true, !nosanitize<br>
- // CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP_IS_UGE_BASE:.*]] = icmp uge i64 %[[COMPUTED_GEP]], 0, !nosanitize<br>
- // CHECK-SANITIZE-NEXT: %[[GEP_DID_NOT_OVERFLOW:.*]] = and i1 %[[COMPUTED_GEP_IS_UGE_BASE]], %[[COMPUTED_OFFSET_DID_NOT_OVERFLOW]], !nosanitize<br>
+ // CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET_IS_UGE_BASE:.*]] = icmp uge i64 %[[COMPUTED_OFFSET]], 0, !nosanitize<br>
+ // CHECK-SANITIZE-NEXT: %[[GEP_DID_NOT_OVERFLOW:.*]] = and i1 %[[COMPUTED_OFFSET_IS_UGE_BASE]], %[[COMPUTED_OFFSET_DID_NOT_OVERFLOW]], !nosanitize<br>
// CHECK-SANITIZE-CPP-NEXT: %[[GEP_IS_OKAY:.*]] = and i1 %[[BOTH_POINTERS_ARE_NULL_OR_BOTH_ARE_NONNULL]], %[[GEP_DID_NOT_OVERFLOW]], !nosanitize<br>
// CHECK-SANITIZE-C-NEXT: br i1 false, label %[[CONT:.*]], label %[[HANDLER_POINTER_OVERFLOW:[^,]+]],{{.*}} !nosanitize<br>
// CHECK-SANITIZE-CPP-NEXT: br i1 %[[GEP_IS_OKAY]], label %[[CONT:.*]], label %[[HANDLER_POINTER_OVERFLOW:[^,]+]],{{.*}} !nosanitize<br>
// CHECK-SANITIZE: [[HANDLER_POINTER_OVERFLOW]]:<br>
- // CHECK-SANITIZE-NORECOVER-NEXT: call void @__ubsan_handle_pointer_overflow_abort(i8* bitcast ({ {{{.*}}} }* @[[LINE_500]] to i8*), i64 0, i64 %[[COMPUTED_GEP]])<br>
- // CHECK-SANITIZE-RECOVER-NEXT: call void @__ubsan_handle_pointer_overflow(i8* bitcast ({ {{{.*}}} }* @[[LINE_500]] to i8*), i64 0, i64 %[[COMPUTED_GEP]])<br>
+ // CHECK-SANITIZE-NORECOVER-NEXT: call void @__ubsan_handle_pointer_overflow_abort(i8* bitcast ({ {{{.*}}} }* @[[LINE_500]] to i8*), i64 0, i64 %[[COMPUTED_OFFSET]])<br>
+ // CHECK-SANITIZE-RECOVER-NEXT: call void @__ubsan_handle_pointer_overflow(i8* bitcast ({ {{{.*}}} }* @[[LINE_500]] to i8*), i64 0, i64 %[[COMPUTED_OFFSET]])<br>
// CHECK-SANITIZE-TRAP-NEXT: call void @llvm.ubsantrap(i8 19){{.*}}, !nosanitize<br>
// CHECK-SANITIZE-UNREACHABLE-NEXT: unreachable, !nosanitize<br>
// CHECK-SANITIZE: [[CONT]]:<br>
<br>
diff --git a/clang/test/CodeGen/complex-convert.c b/clang/test/CodeGen/complex-convert.c<br>
index 14ba5c2ae8e2d..f295cc86f172e 100644<br>
--- a/clang/test/CodeGen/complex-convert.c<br>
+++ b/clang/test/CodeGen/complex-convert.c<br>
@@ -251,9 +251,8 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR100:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR97]] to i[[ARSIZE]]<br>
// CHECK-NEXT: %[[VAR101:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR99]] to i[[ARSIZE]]<br>
// CHECK-NEXT: %[[VAR102:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR95]], %[[VAR100]]<br>
- // CHECK-NEXT: %[[VAR103:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR101]], 0<br>
// CHECK-NEXT: %[[VAR104:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR102]] to i[[CHSIZE]]<br>
- // CHECK-NEXT: %[[VAR105:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR103]] to i[[CHSIZE]]<br>
+ // CHECK-NEXT: %[[VAR105:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR101]] to i[[CHSIZE]]<br>
// CHECK-NEXT: %[[VAR106:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR107:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[CHSIZE]] %[[VAR104]], i[[CHSIZE]]* %[[VAR106]]<br>
@@ -269,9 +268,8 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR114:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR111]] to i[[ARSIZE]]<br>
// CHECK-NEXT: %[[VAR115:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR113]] to i[[ARSIZE]]<br>
// CHECK-NEXT: %[[VAR116:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR109]], %[[VAR114]]<br>
- // CHECK-NEXT: %[[VAR117:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR115]], 0<br>
// CHECK-NEXT: %[[VAR118:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR116]] to i[[CHSIZE]]<br>
- // CHECK-NEXT: %[[VAR119:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR117]] to i[[CHSIZE]]<br>
+ // CHECK-NEXT: %[[VAR119:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR115]] to i[[CHSIZE]]<br>
// CHECK-NEXT: %[[VAR120:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR121:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[CHSIZE]] %[[VAR118]], i[[CHSIZE]]* %[[VAR120]]<br>
@@ -285,11 +283,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR126:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: %[[VAR127:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR126]]<br>
// CHECK-NEXT: %[[VAR128:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR123]], %[[VAR125]]<br>
- // CHECK-NEXT: %[[VAR129:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR127]], 0<br>
// CHECK-NEXT: %[[VAR130:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR131:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR128]], i[[LLSIZE]]* %[[VAR130]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR129]], i[[LLSIZE]]* %[[VAR131]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR127]], i[[LLSIZE]]* %[[VAR131]]<br>
<br>
cull1 = sc + cull;<br>
// CHECK-NEXT: %[[VAR132:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]]<br>
@@ -299,11 +296,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR136:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: %[[VAR137:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR136]]<br>
// CHECK-NEXT: %[[VAR138:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR133]], %[[VAR135]]<br>
- // CHECK-NEXT: %[[VAR139:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR137]], 0<br>
// CHECK-NEXT: %[[VAR140:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR141:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR138]], i[[LLSIZE]]* %[[VAR140]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR139]], i[[LLSIZE]]* %[[VAR141]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR137]], i[[LLSIZE]]* %[[VAR141]]<br>
<br>
csc1 = uc + csc;<br>
// CHECK-NEXT: %[[VAR142:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]]<br>
@@ -315,9 +311,8 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR148:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR145]] to i[[ARSIZE]]<br>
// CHECK-NEXT: %[[VAR149:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR147]] to i[[ARSIZE]]<br>
// CHECK-NEXT: %[[VAR150:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR143]], %[[VAR148]]<br>
- // CHECK-NEXT: %[[VAR151:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR149]], 0<br>
// CHECK-NEXT: %[[VAR152:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR150]] to i[[CHSIZE]]<br>
- // CHECK-NEXT: %[[VAR153:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR151]] to i[[CHSIZE]]<br>
+ // CHECK-NEXT: %[[VAR153:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR149]] to i[[CHSIZE]]<br>
// CHECK-NEXT: %[[VAR154:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR155:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[CHSIZE]] %[[VAR152]], i[[CHSIZE]]* %[[VAR154]]<br>
@@ -333,9 +328,8 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR162:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR159]] to i[[ARSIZE]]<br>
// CHECK-NEXT: %[[VAR163:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR161]] to i[[ARSIZE]]<br>
// CHECK-NEXT: %[[VAR164:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR157]], %[[VAR162]]<br>
- // CHECK-NEXT: %[[VAR165:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR163]], 0<br>
// CHECK-NEXT: %[[VAR166:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR164]] to i[[CHSIZE]]<br>
- // CHECK-NEXT: %[[VAR167:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR165]] to i[[CHSIZE]]<br>
+ // CHECK-NEXT: %[[VAR167:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR163]] to i[[CHSIZE]]<br>
// CHECK-NEXT: %[[VAR168:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR169:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[CHSIZE]] %[[VAR166]], i[[CHSIZE]]* %[[VAR168]]<br>
@@ -349,11 +343,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR174:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: %[[VAR175:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR174]]<br>
// CHECK-NEXT: %[[VAR176:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR171]], %[[VAR173]]<br>
- // CHECK-NEXT: %[[VAR177:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR175]], 0<br>
// CHECK-NEXT: %[[VAR178:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR179:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR176]], i[[LLSIZE]]* %[[VAR178]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR177]], i[[LLSIZE]]* %[[VAR179]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR175]], i[[LLSIZE]]* %[[VAR179]]<br>
<br>
cull1 = uc + cull;<br>
// CHECK-NEXT: %[[VAR180:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]]<br>
@@ -363,11 +356,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR184:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: %[[VAR185:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR184]]<br>
// CHECK-NEXT: %[[VAR186:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR181]], %[[VAR183]]<br>
- // CHECK-NEXT: %[[VAR187:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR185]], 0<br>
// CHECK-NEXT: %[[VAR188:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR189:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR186]], i[[LLSIZE]]* %[[VAR188]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR187]], i[[LLSIZE]]* %[[VAR189]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR185]], i[[LLSIZE]]* %[[VAR189]]<br>
<br>
csll1 = sll + csc;<br>
// CHECK-NEXT: %[[VAR190:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]]<br>
@@ -378,11 +370,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR195:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR192]] to i[[LLSIZE]]<br>
// CHECK-NEXT: %[[VAR196:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR194]] to i[[LLSIZE]]<br>
// CHECK-NEXT: %[[VAR197:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR190]], %[[VAR195]]<br>
- // CHECK-NEXT: %[[VAR198:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR196]], 0<br>
// CHECK-NEXT: %[[VAR199:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR200:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR197]], i[[LLSIZE]]* %[[VAR199]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR198]], i[[LLSIZE]]* %[[VAR200]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR196]], i[[LLSIZE]]* %[[VAR200]]<br>
<br>
csll1 = sll + cuc;<br>
// CHECK-NEXT: %[[VAR201:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]]<br>
@@ -393,11 +384,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR206:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR203]] to i[[LLSIZE]]<br>
// CHECK-NEXT: %[[VAR207:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR205]] to i[[LLSIZE]]<br>
// CHECK-NEXT: %[[VAR208:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR201]], %[[VAR206]]<br>
- // CHECK-NEXT: %[[VAR209:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR207]], 0<br>
// CHECK-NEXT: %[[VAR210:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR211:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR208]], i[[LLSIZE]]* %[[VAR210]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR209]], i[[LLSIZE]]* %[[VAR211]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR207]], i[[LLSIZE]]* %[[VAR211]]<br>
<br>
csll1 = sll + csll;<br>
// CHECK-NEXT: %[[VAR212:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]]<br>
@@ -406,11 +396,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR215:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: %[[VAR216:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR215]]<br>
// CHECK-NEXT: %[[VAR217:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR212]], %[[VAR214]]<br>
- // CHECK-NEXT: %[[VAR218:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR216]], 0<br>
// CHECK-NEXT: %[[VAR219:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR220:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR217]], i[[LLSIZE]]* %[[VAR219]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR218]], i[[LLSIZE]]* %[[VAR220]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR216]], i[[LLSIZE]]* %[[VAR220]]<br>
<br>
csll1 = sll + cull;<br>
// CHECK-NEXT: %[[VAR221:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]]<br>
@@ -419,11 +408,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR224:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: %[[VAR225:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR224]]<br>
// CHECK-NEXT: %[[VAR226:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR221]], %[[VAR223]]<br>
- // CHECK-NEXT: %[[VAR227:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR225]], 0<br>
// CHECK-NEXT: %[[VAR228:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR229:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR226]], i[[LLSIZE]]* %[[VAR228]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR227]], i[[LLSIZE]]* %[[VAR229]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR225]], i[[LLSIZE]]* %[[VAR229]]<br>
<br>
csll1 = ull + csc;<br>
// CHECK-NEXT: %[[VAR230:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]]<br>
@@ -434,11 +422,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR235:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR232]] to i[[LLSIZE]]<br>
// CHECK-NEXT: %[[VAR236:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR234]] to i[[LLSIZE]]<br>
// CHECK-NEXT: %[[VAR237:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR230]], %[[VAR235]]<br>
- // CHECK-NEXT: %[[VAR238:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR236]], 0<br>
// CHECK-NEXT: %[[VAR239:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR240:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR237]], i[[LLSIZE]]* %[[VAR239]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR238]], i[[LLSIZE]]* %[[VAR240]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR236]], i[[LLSIZE]]* %[[VAR240]]<br>
<br>
cull1 = ull + cuc;<br>
// CHECK-NEXT: %[[VAR241:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]]<br>
@@ -449,11 +436,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR246:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR243]] to i[[LLSIZE]]<br>
// CHECK-NEXT: %[[VAR247:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR245]] to i[[LLSIZE]]<br>
// CHECK-NEXT: %[[VAR248:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR241]], %[[VAR246]]<br>
- // CHECK-NEXT: %[[VAR249:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR247]], 0<br>
// CHECK-NEXT: %[[VAR250:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR251:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR248]], i[[LLSIZE]]* %[[VAR250]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR249]], i[[LLSIZE]]* %[[VAR251]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR247]], i[[LLSIZE]]* %[[VAR251]]<br>
<br>
csll1 = ull + csll;<br>
// CHECK-NEXT: %[[VAR252:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]]<br>
@@ -462,11 +448,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR255:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: %[[VAR256:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR255]]<br>
// CHECK-NEXT: %[[VAR257:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR252]], %[[VAR254]]<br>
- // CHECK-NEXT: %[[VAR258:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR256]], 0<br>
// CHECK-NEXT: %[[VAR259:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR260:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR257]], i[[LLSIZE]]* %[[VAR259]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR258]], i[[LLSIZE]]* %[[VAR260]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR256]], i[[LLSIZE]]* %[[VAR260]]<br>
<br>
cull1 = ull + cull;<br>
// CHECK-NEXT: %[[VAR261:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]]<br>
@@ -475,11 +460,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR264:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: %[[VAR265:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR264]]<br>
// CHECK-NEXT: %[[VAR266:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR261]], %[[VAR263]]<br>
- // CHECK-NEXT: %[[VAR267:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR265]], 0<br>
// CHECK-NEXT: %[[VAR268:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR269:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR266]], i[[LLSIZE]]* %[[VAR268]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR267]], i[[LLSIZE]]* %[[VAR269]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR265]], i[[LLSIZE]]* %[[VAR269]]<br>
<br>
csc1 = csc + sc;<br>
// CHECK-NEXT: %[[VAR270:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
@@ -491,9 +475,8 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR276:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]]<br>
// CHECK-NEXT: %[[VAR277:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR276]] to i[[ARSIZE]]<br>
// CHECK-NEXT: %[[VAR278:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR274]], %[[VAR277]]<br>
- // CHECK-NEXT: %[[VAR279:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR275]], 0<br>
// CHECK-NEXT: %[[VAR280:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR278]] to i[[CHSIZE]]<br>
- // CHECK-NEXT: %[[VAR281:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR279]] to i[[CHSIZE]]<br>
+ // CHECK-NEXT: %[[VAR281:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR275]] to i[[CHSIZE]]<br>
// CHECK-NEXT: %[[VAR282:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR283:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[CHSIZE]] %[[VAR280]], i[[CHSIZE]]* %[[VAR282]]<br>
@@ -509,9 +492,8 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR290:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]]<br>
// CHECK-NEXT: %[[VAR291:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR290]] to i[[ARSIZE]]<br>
// CHECK-NEXT: %[[VAR292:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR288]], %[[VAR291]]<br>
- // CHECK-NEXT: %[[VAR293:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR289]], 0<br>
// CHECK-NEXT: %[[VAR294:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR292]] to i[[CHSIZE]]<br>
- // CHECK-NEXT: %[[VAR295:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR293]] to i[[CHSIZE]]<br>
+ // CHECK-NEXT: %[[VAR295:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR289]] to i[[CHSIZE]]<br>
// CHECK-NEXT: %[[VAR296:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR297:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[CHSIZE]] %[[VAR294]], i[[CHSIZE]]* %[[VAR296]]<br>
@@ -526,11 +508,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR303:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR301]] to i[[LLSIZE]]<br>
// CHECK-NEXT: %[[VAR304:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]]<br>
// CHECK-NEXT: %[[VAR305:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR302]], %[[VAR304]]<br>
- // CHECK-NEXT: %[[VAR306:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR303]], 0<br>
// CHECK-NEXT: %[[VAR307:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR308:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR305]], i[[LLSIZE]]* %[[VAR307]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR306]], i[[LLSIZE]]* %[[VAR308]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR303]], i[[LLSIZE]]* %[[VAR308]]<br>
<br>
csll1 = csc + ull;<br>
// CHECK-NEXT: %[[VAR309:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
@@ -541,11 +522,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR314:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR312]] to i[[LLSIZE]]<br>
// CHECK-NEXT: %[[VAR315:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]]<br>
// CHECK-NEXT: %[[VAR316:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR313]], %[[VAR315]]<br>
- // CHECK-NEXT: %[[VAR317:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR314]], 0<br>
// CHECK-NEXT: %[[VAR318:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR319:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR316]], i[[LLSIZE]]* %[[VAR318]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR317]], i[[LLSIZE]]* %[[VAR319]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR314]], i[[LLSIZE]]* %[[VAR319]]<br>
<br>
csc1 = cuc + sc;<br>
// CHECK-NEXT: %[[VAR320:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
@@ -557,9 +537,8 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR326:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]]<br>
// CHECK-NEXT: %[[VAR327:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR326]] to i[[ARSIZE]]<br>
// CHECK-NEXT: %[[VAR328:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR324]], %[[VAR327]]<br>
- // CHECK-NEXT: %[[VAR329:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR325]], 0<br>
// CHECK-NEXT: %[[VAR330:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR328]] to i[[CHSIZE]]<br>
- // CHECK-NEXT: %[[VAR331:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR329]] to i[[CHSIZE]]<br>
+ // CHECK-NEXT: %[[VAR331:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR325]] to i[[CHSIZE]]<br>
// CHECK-NEXT: %[[VAR332:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR333:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[CHSIZE]] %[[VAR330]], i[[CHSIZE]]* %[[VAR332]]<br>
@@ -575,9 +554,8 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR340:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]]<br>
// CHECK-NEXT: %[[VAR341:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR340]] to i[[ARSIZE]]<br>
// CHECK-NEXT: %[[VAR342:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR338]], %[[VAR341]]<br>
- // CHECK-NEXT: %[[VAR343:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR339]], 0<br>
// CHECK-NEXT: %[[VAR344:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR342]] to i[[CHSIZE]]<br>
- // CHECK-NEXT: %[[VAR345:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR343]] to i[[CHSIZE]]<br>
+ // CHECK-NEXT: %[[VAR345:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR339]] to i[[CHSIZE]]<br>
// CHECK-NEXT: %[[VAR346:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR347:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[CHSIZE]] %[[VAR344]], i[[CHSIZE]]* %[[VAR346]]<br>
@@ -592,11 +570,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR353:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR351]] to i[[LLSIZE]]<br>
// CHECK-NEXT: %[[VAR354:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]]<br>
// CHECK-NEXT: %[[VAR355:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR352]], %[[VAR354]]<br>
- // CHECK-NEXT: %[[VAR356:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR353]], 0<br>
// CHECK-NEXT: %[[VAR357:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR358:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR355]], i[[LLSIZE]]* %[[VAR357]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR356]], i[[LLSIZE]]* %[[VAR358]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR353]], i[[LLSIZE]]* %[[VAR358]]<br>
<br>
cull1 = cuc + ull;<br>
// CHECK-NEXT: %[[VAR357:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
@@ -607,11 +584,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR362:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR360]] to i[[LLSIZE]]<br>
// CHECK-NEXT: %[[VAR363:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]]<br>
// CHECK-NEXT: %[[VAR364:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR361]], %[[VAR363]]<br>
- // CHECK-NEXT: %[[VAR365:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR362]], 0<br>
// CHECK-NEXT: %[[VAR366:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR367:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR364]], i[[LLSIZE]]* %[[VAR366]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR365]], i[[LLSIZE]]* %[[VAR367]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR362]], i[[LLSIZE]]* %[[VAR367]]<br>
<br>
csll1 = csll + sc;<br>
// CHECK-NEXT: %[[VAR368:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
@@ -621,11 +597,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR372:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]]<br>
// CHECK-NEXT: %[[VAR373:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR372]] to i[[LLSIZE]]<br>
// CHECK-NEXT: %[[VAR374:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR369]], %[[VAR373]]<br>
- // CHECK-NEXT: %[[VAR375:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR371]], 0<br>
// CHECK-NEXT: %[[VAR376:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR377:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR374]], i[[LLSIZE]]* %[[VAR376]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR375]], i[[LLSIZE]]* %[[VAR377]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR371]], i[[LLSIZE]]* %[[VAR377]]<br>
<br>
csll1 = csll + uc;<br>
// CHECK-NEXT: %[[VAR378:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
@@ -635,11 +610,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR382:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]]<br>
// CHECK-NEXT: %[[VAR383:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR382]] to i[[LLSIZE]]<br>
// CHECK-NEXT: %[[VAR384:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR379]], %[[VAR383]]<br>
- // CHECK-NEXT: %[[VAR385:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR381]], 0<br>
// CHECK-NEXT: %[[VAR386:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR387:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR384]], i[[LLSIZE]]* %[[VAR386]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR385]], i[[LLSIZE]]* %[[VAR387]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR381]], i[[LLSIZE]]* %[[VAR387]]<br>
<br>
csll1 = csll + sll;<br>
// CHECK-NEXT: %[[VAR388:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
@@ -648,11 +622,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR391:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR390]]<br>
// CHECK-NEXT: %[[VAR392:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]]<br>
// CHECK-NEXT: %[[VAR393:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR389]], %[[VAR392]]<br>
- // CHECK-NEXT: %[[VAR394:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR391]], 0<br>
// CHECK-NEXT: %[[VAR395:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR396:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR393]], i[[LLSIZE]]* %[[VAR395]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR394]], i[[LLSIZE]]* %[[VAR396]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR391]], i[[LLSIZE]]* %[[VAR396]]<br>
<br>
csll1 = csll + ull;<br>
// CHECK-NEXT: %[[VAR397:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
@@ -661,11 +634,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR400:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR399]]<br>
// CHECK-NEXT: %[[VAR401:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]]<br>
// CHECK-NEXT: %[[VAR402:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR398]], %[[VAR401]]<br>
- // CHECK-NEXT: %[[VAR403:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR400]], 0<br>
// CHECK-NEXT: %[[VAR404:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR405:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR402]], i[[LLSIZE]]* %[[VAR404]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR403]], i[[LLSIZE]]* %[[VAR405]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR400]], i[[LLSIZE]]* %[[VAR405]]<br>
<br>
csll1 = cull + sc;<br>
// CHECK-NEXT: %[[VAR406:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
@@ -675,11 +647,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR410:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]]<br>
// CHECK-NEXT: %[[VAR411:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR410]] to i[[LLSIZE]]<br>
// CHECK-NEXT: %[[VAR412:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR407]], %[[VAR411]]<br>
- // CHECK-NEXT: %[[VAR413:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR409]], 0<br>
// CHECK-NEXT: %[[VAR414:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR415:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR412]], i[[LLSIZE]]* %[[VAR414]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR413]], i[[LLSIZE]]* %[[VAR415]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR409]], i[[LLSIZE]]* %[[VAR415]]<br>
<br>
cull1 = cull + uc;<br>
// CHECK-NEXT: %[[VAR416:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
@@ -689,11 +660,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR420:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]]<br>
// CHECK-NEXT: %[[VAR421:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR420]] to i[[LLSIZE]]<br>
// CHECK-NEXT: %[[VAR422:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR417]], %[[VAR421]]<br>
- // CHECK-NEXT: %[[VAR423:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR419]], 0<br>
// CHECK-NEXT: %[[VAR424:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR425:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR422]], i[[LLSIZE]]* %[[VAR424]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR423]], i[[LLSIZE]]* %[[VAR425]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR419]], i[[LLSIZE]]* %[[VAR425]]<br>
<br>
csll1 = cull + sll;<br>
// CHECK-NEXT: %[[VAR426:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
@@ -702,11 +672,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR429:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR428]]<br>
// CHECK-NEXT: %[[VAR430:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]]<br>
// CHECK-NEXT: %[[VAR431:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR427]], %[[VAR430]]<br>
- // CHECK-NEXT: %[[VAR432:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR429]], 0<br>
// CHECK-NEXT: %[[VAR433:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR434:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR431]], i[[LLSIZE]]* %[[VAR433]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR432]], i[[LLSIZE]]* %[[VAR434]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR429]], i[[LLSIZE]]* %[[VAR434]]<br>
<br>
cull1 = cull + ull;<br>
// CHECK-NEXT: %[[VAR435:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
@@ -715,11 +684,10 @@ void foo(signed char sc, unsigned char uc, signed long long sll,<br>
// CHECK-NEXT: %[[VAR438:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR437]]<br>
// CHECK-NEXT: %[[VAR439:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]]<br>
// CHECK-NEXT: %[[VAR440:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR436]], %[[VAR439]]<br>
- // CHECK-NEXT: %[[VAR441:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR438]], 0<br>
// CHECK-NEXT: %[[VAR442:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0<br>
// CHECK-NEXT: %[[VAR443:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1<br>
// CHECK-NEXT: store i[[LLSIZE]] %[[VAR440]], i[[LLSIZE]]* %[[VAR442]]<br>
- // CHECK-NEXT: store i[[LLSIZE]] %[[VAR441]], i[[LLSIZE]]* %[[VAR443]]<br>
+ // CHECK-NEXT: store i[[LLSIZE]] %[[VAR438]], i[[LLSIZE]]* %[[VAR443]]<br>
}<br>
<br>
// This code used to cause a crash; test that it no longer does so.<br>
<br>
diff --git a/clang/test/CodeGen/matrix-type-operators.c b/clang/test/CodeGen/matrix-type-operators.c<br>
index 8f6bc7e87a1ba..b108e09905504 100644<br>
--- a/clang/test/CodeGen/matrix-type-operators.c<br>
+++ b/clang/test/CodeGen/matrix-type-operators.c<br>
@@ -1039,11 +1039,10 @@ void insert_extract(dx5x5_t a, fx3x3_t b, unsigned long j, short k) {<br>
// CHECK: [[K:%.*]] = load i16, i16* %k.addr, align 2<br>
// CHECK-NEXT: [[K_EXT:%.*]] = sext i16 [[K]] to i64<br>
// CHECK-NEXT: [[IDX1:%.*]] = mul i64 [[K_EXT]], 3<br>
- // CHECK-NEXT: [[IDX2:%.*]] = add i64 [[IDX1]], 0<br>
- // OPT-NEXT: [[CMP:%.*]] = icmp ult i64 [[IDX2]], 9<br>
+ // OPT-NEXT: [[CMP:%.*]] = icmp ult i64 [[IDX1]], 9<br>
// OPT-NEXT: call void @llvm.assume(i1 [[CMP]])<br>
// CHECK-NEXT: [[MAT:%.*]] = load <9 x float>, <9 x float>* [[MAT_ADDR:%.*]], align 4<br>
- // CHECK-NEXT: [[MATEXT:%.*]] = extractelement <9 x float> [[MAT]], i64 [[IDX2]]<br>
+ // CHECK-NEXT: [[MATEXT:%.*]] = extractelement <9 x float> [[MAT]], i64 [[IDX1]]<br>
// CHECK-NEXT: [[J:%.*]] = load i64, i64* %j.addr, align 8<br>
// CHECK-NEXT: [[IDX3:%.*]] = mul i64 [[J]], 3<br>
// CHECK-NEXT: [[IDX4:%.*]] = add i64 [[IDX3]], 2<br>
<br>
diff --git a/clang/test/CodeGen/volatile-1.c b/clang/test/CodeGen/volatile-1.c<br>
index a0c7093363d70..2e5983f8a8999 100644<br>
--- a/clang/test/CodeGen/volatile-1.c<br>
+++ b/clang/test/CodeGen/volatile-1.c<br>
@@ -201,7 +201,7 @@ void test() {<br>
__real (i = j);<br>
// CHECK-NEXT: load volatile<br>
__imag i;<br>
- <br>
+<br>
// ============================================================<br>
// FIXME: Test cases we get wrong.<br>
<br>
@@ -219,7 +219,7 @@ void test() {<br>
// CHECK-NEXT: call void @llvm.memcpy{{.*}}, i1 true<br>
((a=a),a);<br>
<br>
- // Not a use. gcc gets this wrong, it doesn't emit the copy! <br>
+ // Not a use. gcc gets this wrong, it doesn't emit the copy!<br>
// (void)(a=a);<br>
<br>
// Not a use. gcc got this wrong in 4.2 and omitted the side effects<br>
@@ -278,7 +278,7 @@ void test() {<br>
// A use.<br>
// CHECK-NEXT: load volatile<br>
// CHECK-NEXT: add<br>
- i + 0;<br>
+ i + 1;<br>
// A use.<br>
// CHECK-NEXT: load volatile<br>
// CHECK-NEXT: store volatile<br>
@@ -290,7 +290,7 @@ void test() {<br>
// CHECK-NEXT: load volatile<br>
// CHECK-NEXT: store volatile<br>
// CHECK-NEXT: add<br>
- (i=j) + 0;<br>
+ (i=j) + 1;<br>
<br>
#ifdef __cplusplus<br>
(i,j)=k;<br>
@@ -320,7 +320,6 @@ int test2() {<br>
// CHECK-NEXT: load volatile i32, i32*<br>
// CHECK-NEXT: load volatile i32, i32*<br>
// CHECK-NEXT: add i32<br>
- // CHECK-NEXT: add i32<br>
// CHECK-NEXT: store volatile i32<br>
// CHECK-NEXT: ret i32<br>
return i += ci;<br>
<br>
diff --git a/clang/test/CodeGenCXX/microsoft-abi-virtual-inheritance.cpp b/clang/test/CodeGenCXX/microsoft-abi-virtual-inheritance.cpp<br>
index 06194e4a30431..99ae065427d63 100644<br>
--- a/clang/test/CodeGenCXX/microsoft-abi-virtual-inheritance.cpp<br>
+++ b/clang/test/CodeGenCXX/microsoft-abi-virtual-inheritance.cpp<br>
@@ -39,10 +39,9 @@ B::B() {<br>
// CHECK: %[[THIS_i8:.*]] = bitcast %struct.B* %[[THIS]] to i8*<br>
// CHECK: %[[VBPTR:.*]] = getelementptr inbounds i8, i8* %[[THIS_i8]], i32 0<br>
// ...<br>
- // CHECK: %[[VBASE_OFFSET:.*]] = add nsw i32 %{{.*}}, 0<br>
- // CHECK: %[[VTORDISP_VAL:.*]] = sub i32 %[[VBASE_OFFSET]], 8<br>
+ // CHECK: %[[VTORDISP_VAL:.*]] = sub i32 %{{.*}}, 8<br>
// CHECK: %[[THIS_i8:.*]] = bitcast %struct.B* %[[THIS]] to i8*<br>
- // CHECK: %[[VBASE_i8:.*]] = getelementptr inbounds i8, i8* %[[THIS_i8]], i32 %[[VBASE_OFFSET]]<br>
+ // CHECK: %[[VBASE_i8:.*]] = getelementptr inbounds i8, i8* %[[THIS_i8]], i32 %{{.*}}<br>
// CHECK: %[[VTORDISP_i8:.*]] = getelementptr i8, i8* %[[VBASE_i8]], i32 -4<br>
// CHECK: %[[VTORDISP_PTR:.*]] = bitcast i8* %[[VTORDISP_i8]] to i32*<br>
// CHECK: store i32 %[[VTORDISP_VAL]], i32* %[[VTORDISP_PTR]]<br>
@@ -74,10 +73,9 @@ B::~B() {<br>
// CHECK: %[[THIS_i8:.*]] = bitcast %struct.B* %[[THIS]] to i8*<br>
// CHECK: %[[VBPTR:.*]] = getelementptr inbounds i8, i8* %[[THIS_i8]], i32 0<br>
// ...<br>
- // CHECK: %[[VBASE_OFFSET:.*]] = add nsw i32 %{{.*}}, 0<br>
- // CHECK: %[[VTORDISP_VAL:.*]] = sub i32 %[[VBASE_OFFSET]], 8<br>
+ // CHECK: %[[VTORDISP_VAL:.*]] = sub i32 %{{.*}}, 8<br>
// CHECK: %[[THIS_i8:.*]] = bitcast %struct.B* %[[THIS]] to i8*<br>
- // CHECK: %[[VBASE_i8:.*]] = getelementptr inbounds i8, i8* %[[THIS_i8]], i32 %[[VBASE_OFFSET]]<br>
+ // CHECK: %[[VBASE_i8:.*]] = getelementptr inbounds i8, i8* %[[THIS_i8]], i32 %{{.*}}<br>
// CHECK: %[[VTORDISP_i8:.*]] = getelementptr i8, i8* %[[VBASE_i8]], i32 -4<br>
// CHECK: %[[VTORDISP_PTR:.*]] = bitcast i8* %[[VTORDISP_i8]] to i32*<br>
// CHECK: store i32 %[[VTORDISP_VAL]], i32* %[[VTORDISP_PTR]]<br>
@@ -138,9 +136,8 @@ void B::foo() {<br>
// CHECK: %[[VBTABLE:.*]] = load i32*, i32** %[[VBPTR8]]<br>
// CHECK: %[[VBENTRY:.*]] = getelementptr inbounds i32, i32* %[[VBTABLE]], i32 1<br>
// CHECK: %[[VBOFFSET32:.*]] = load i32, i32* %[[VBENTRY]]<br>
-// CHECK: %[[VBOFFSET:.*]] = add nsw i32 %[[VBOFFSET32]], 0<br>
// CHECK: %[[THIS8:.*]] = bitcast %struct.B* %[[THIS]] to i8*<br>
-// CHECK: %[[VBASE_i8:.*]] = getelementptr inbounds i8, i8* %[[THIS8]], i32 %[[VBOFFSET]]<br>
+// CHECK: %[[VBASE_i8:.*]] = getelementptr inbounds i8, i8* %[[THIS8]], i32 %[[VBOFFSET32]]<br>
// CHECK: %[[VBASE:.*]] = bitcast i8* %[[VBASE_i8]] to %struct.VBase*<br>
// CHECK: %[[FIELD:.*]] = getelementptr inbounds %struct.VBase, %struct.VBase* %[[VBASE]], i32 0, i32 1<br>
// CHECK: store i32 42, i32* %[[FIELD]], align 4<br>
@@ -162,8 +159,7 @@ void call_vbase_bar(B *obj) {<br>
// CHECK: %[[VBTABLE:.*]] = load i32*, i32** %[[VBPTR8]]<br>
// CHECK: %[[VBENTRY:.*]] = getelementptr inbounds i32, i32* %[[VBTABLE]], i32 1<br>
// CHECK: %[[VBOFFSET32:.*]] = load i32, i32* %[[VBENTRY]]<br>
-// CHECK: %[[VBOFFSET:.*]] = add nsw i32 %[[VBOFFSET32]], 0<br>
-// CHECK: %[[VBASE:.*]] = getelementptr inbounds i8, i8* %[[OBJ_i8]], i32 %[[VBOFFSET]]<br>
+// CHECK: %[[VBASE:.*]] = getelementptr inbounds i8, i8* %[[OBJ_i8]], i32 %[[VBOFFSET32]]<br>
//<br>
// CHECK: %[[OBJ_i8:.*]] = bitcast %struct.B* %[[OBJ]] to i8*<br>
// CHECK: %[[VBPTR:.*]] = getelementptr inbounds i8, i8* %[[OBJ_i8]], i32 0<br>
@@ -171,8 +167,7 @@ void call_vbase_bar(B *obj) {<br>
// CHECK: %[[VBTABLE:.*]] = load i32*, i32** %[[VBPTR8]]<br>
// CHECK: %[[VBENTRY:.*]] = getelementptr inbounds i32, i32* %[[VBTABLE]], i32 1<br>
// CHECK: %[[VBOFFSET32:.*]] = load i32, i32* %[[VBENTRY]]<br>
-// CHECK: %[[VBOFFSET:.*]] = add nsw i32 %[[VBOFFSET32]], 0<br>
-// CHECK: %[[VBASE_i8:.*]] = getelementptr inbounds i8, i8* %[[OBJ_i8]], i32 %[[VBOFFSET]]<br>
+// CHECK: %[[VBASE_i8:.*]] = getelementptr inbounds i8, i8* %[[OBJ_i8]], i32 %[[VBOFFSET32]]<br>
// CHECK: %[[VFPTR:.*]] = bitcast i8* %[[VBASE_i8]] to void (i8*)***<br>
// CHECK: %[[VFTABLE:.*]] = load void (i8*)**, void (i8*)*** %[[VFPTR]]<br>
// CHECK: %[[VFUN:.*]] = getelementptr inbounds void (i8*)*, void (i8*)** %[[VFTABLE]], i64 2<br>
@@ -194,8 +189,7 @@ void delete_B(B *obj) {<br>
// CHECK: %[[VBTABLE:.*]] = load i32*, i32** %[[VBPTR8]]<br>
// CHECK: %[[VBENTRY:.*]] = getelementptr inbounds i32, i32* %[[VBTABLE]], i32 1<br>
// CHECK: %[[VBOFFSET32:.*]] = load i32, i32* %[[VBENTRY]]<br>
-// CHECK: %[[VBOFFSET:.*]] = add nsw i32 %[[VBOFFSET32]], 0<br>
-// CHECK: %[[VBASE_i8:.*]] = getelementptr inbounds i8, i8* %[[OBJ_i8]], i32 %[[VBOFFSET]]<br>
+// CHECK: %[[VBASE_i8:.*]] = getelementptr inbounds i8, i8* %[[OBJ_i8]], i32 %[[VBOFFSET32]]<br>
// CHECK: %[[VBASE:.*]] = bitcast i8* %[[VBASE_i8]] to %struct.B*<br>
//<br>
// CHECK: %[[OBJ_i8:.*]] = bitcast %struct.B* %[[OBJ]] to i8*<br>
@@ -204,8 +198,7 @@ void delete_B(B *obj) {<br>
// CHECK: %[[VBTABLE:.*]] = load i32*, i32** %[[VBPTR8]]<br>
// CHECK: %[[VBENTRY:.*]] = getelementptr inbounds i32, i32* %[[VBTABLE]], i32 1<br>
// CHECK: %[[VBOFFSET32:.*]] = load i32, i32* %[[VBENTRY]]<br>
-// CHECK: %[[VBOFFSET:.*]] = add nsw i32 %[[VBOFFSET32]], 0<br>
-// CHECK: %[[VBASE_i8:.*]] = getelementptr inbounds i8, i8* %[[OBJ_i8]], i32 %[[VBOFFSET]]<br>
+// CHECK: %[[VBASE_i8:.*]] = getelementptr inbounds i8, i8* %[[OBJ_i8]], i32 %[[VBOFFSET32]]<br>
// CHECK: %[[VFPTR:.*]] = bitcast i8* %[[VBASE_i8]] to i8* (%struct.B*, i32)***<br>
// CHECK: %[[VFTABLE:.*]] = load i8* (%struct.B*, i32)**, i8* (%struct.B*, i32)*** %[[VFPTR]]<br>
// CHECK: %[[VFUN:.*]] = getelementptr inbounds i8* (%struct.B*, i32)*, i8* (%struct.B*, i32)** %[[VFTABLE]], i64 0<br>
<br>
diff --git a/clang/test/CodeGenCXX/virtual-base-cast.cpp b/clang/test/CodeGenCXX/virtual-base-cast.cpp<br>
index 9cde81ee05de9..466b0933ec12c 100644<br>
--- a/clang/test/CodeGenCXX/virtual-base-cast.cpp<br>
+++ b/clang/test/CodeGenCXX/virtual-base-cast.cpp<br>
@@ -24,7 +24,6 @@ A* a() { return x; }<br>
// MSVC: %[[vbtable:.*]] = load i32*, i32** %[[vbptr]]<br>
// MSVC: %[[entry:.*]] = getelementptr inbounds i32, i32* {{.*}}, i32 1<br>
// MSVC: %[[offset:.*]] = load i32, i32* %[[entry]]<br>
-// MSVC: add nsw i32 %[[offset]], 0<br>
// MSVC: }<br>
<br>
B* b() { return x; }<br>
@@ -41,7 +40,6 @@ B* b() { return x; }<br>
// MSVC: %[[vbtable:.*]] = load i32*, i32** %[[vbptr]]<br>
// MSVC: %[[entry:.*]] = getelementptr inbounds i32, i32* {{.*}}, i32 2<br>
// MSVC: %[[offset:.*]] = load i32, i32* %[[entry]]<br>
-// MSVC: add nsw i32 %[[offset]], 0<br>
// MSVC: }<br>
<br>
<br>
@@ -60,7 +58,6 @@ BB* c() { return x; }<br>
// MSVC: %[[vbtable:.*]] = load i32*, i32** %[[vbptr]]<br>
// MSVC: %[[entry:.*]] = getelementptr inbounds i32, i32* {{.*}}, i32 4<br>
// MSVC: %[[offset:.*]] = load i32, i32* %[[entry]]<br>
-// MSVC: add nsw i32 %[[offset]], 0<br>
// MSVC: }<br>
<br>
// Put the vbptr at a non-zero offset inside a non-virtual base.<br>
<br>
diff --git a/clang/test/CodeGenCXX/volatile-1.cpp b/clang/test/CodeGenCXX/volatile-1.cpp<br>
index 525e828da3934..db2155cc5fe8b 100644<br>
--- a/clang/test/CodeGenCXX/volatile-1.cpp<br>
+++ b/clang/test/CodeGenCXX/volatile-1.cpp<br>
@@ -248,7 +248,7 @@ void test() {<br>
// CHECK-NEXT: store volatile<br>
<br>
__imag i;<br>
- <br>
+<br>
// ============================================================<br>
// FIXME: Test cases we get wrong.<br>
<br>
@@ -264,7 +264,7 @@ void test() {<br>
// CHECK-NEXT: call {{.*}}void<br>
((a=a),a);<br>
<br>
- // Not a use. gcc gets this wrong, it doesn't emit the copy! <br>
+ // Not a use. gcc gets this wrong, it doesn't emit the copy!<br>
// CHECK-NEXT: call {{.*}}void<br>
(void)(a=a);<br>
<br>
@@ -331,7 +331,7 @@ void test() {<br>
// CHECK-NEXT: store volatile<br>
<br>
// A use.<br>
- i + 0;<br>
+ i + 1;<br>
// CHECK-NEXT: load volatile<br>
// CHECK-NEXT: add<br>
<br>
@@ -345,7 +345,7 @@ void test() {<br>
<br>
// A use. gcc treats this as not a use, that's probably a bug due to tree<br>
// folding ignoring volatile.<br>
- (i=j) + 0;<br>
+ (i=j) + 1;<br>
// CHECK-NEXT: load volatile<br>
// CHECK-NEXT: store volatile<br>
// CHECK-NEXT: load volatile<br>
<br>
diff --git a/clang/test/CodeGenOpenCLCXX/addrspace-operators.clcpp b/clang/test/CodeGenOpenCLCXX/addrspace-operators.clcpp<br>
index bd3832635d9b1..b15a12463d292 100644<br>
--- a/clang/test/CodeGenOpenCLCXX/addrspace-operators.clcpp<br>
+++ b/clang/test/CodeGenOpenCLCXX/addrspace-operators.clcpp<br>
@@ -34,7 +34,7 @@ void bar() {<br>
//CHECK: store i32 %or, i32 addrspace(1)* @globI<br>
globI |= b;<br>
//CHECK: store i32 %add, i32 addrspace(1)* @globI<br>
- globI += a;<br>
+ globI += b;<br>
//CHECK: [[GVIV1:%[0-9]+]] = load volatile i32, i32 addrspace(1)* @globVI<br>
//CHECK: [[AND:%[a-z0-9]+]] = and i32 [[GVIV1]], 1<br>
//CHECK: store volatile i32 [[AND]], i32 addrspace(1)* @globVI<br>
<br>
diff --git a/llvm/include/llvm/IR/IRBuilder.h b/llvm/include/llvm/IR/IRBuilder.h<br>
index d2a2f947adac3..5bbeb5727adc1 100644<br>
--- a/llvm/include/llvm/IR/IRBuilder.h<br>
+++ b/llvm/include/llvm/IR/IRBuilder.h<br>
@@ -1213,6 +1213,9 @@ class IRBuilderBase {<br>
bool HasNUW = false, bool HasNSW = false) {<br>
if (!isa<Constant>(RHS) && isa<Constant>(LHS))<br>
std::swap(LHS, RHS);<br>
+ if (auto RCI = dyn_cast<ConstantInt>(RHS))<br>
+ if (RCI->isZero())<br>
+ return LHS; // LHS + 0 -> LHS<br>
if (auto *LC = dyn_cast<Constant>(LHS))<br>
if (auto *RC = dyn_cast<Constant>(RHS))<br>
return Insert(Folder.CreateAdd(LC, RC, HasNUW, HasNSW), Name);<br>
<br>
diff --git a/llvm/test/Instrumentation/AddressSanitizer/fake-stack.ll b/llvm/test/Instrumentation/AddressSanitizer/fake-stack.ll<br>
index b64d67bdc4bc9..6272ac92109e4 100644<br>
--- a/llvm/test/Instrumentation/AddressSanitizer/fake-stack.ll<br>
+++ b/llvm/test/Instrumentation/AddressSanitizer/fake-stack.ll<br>
@@ -33,14 +33,12 @@ define void @Simple() uwtable sanitize_address {<br>
; NEVER-NEXT: store i64 ptrtoint (void ()* @Simple to i64), i64* [[TMP7]], align 8<br>
; NEVER-NEXT: [[TMP8:%.*]] = lshr i64 [[TMP0]], 3<br>
; NEVER-NEXT: [[TMP9:%.*]] = add i64 [[TMP8]], 2147450880<br>
-; NEVER-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 0<br>
-; NEVER-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to i64*<br>
-; NEVER-NEXT: store i64 -868083113472691727, i64* [[TMP11]], align 1<br>
+; NEVER-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to i64*<br>
+; NEVER-NEXT: store i64 -868083113472691727, i64* [[TMP10]], align 1<br>
; NEVER-NEXT: call void @Foo(i8* [[TMP2]])<br>
; NEVER-NEXT: store i64 1172321806, i64* [[TMP3]], align 8<br>
-; NEVER-NEXT: [[TMP12:%.*]] = add i64 [[TMP9]], 0<br>
-; NEVER-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to i64*<br>
-; NEVER-NEXT: store i64 0, i64* [[TMP13]], align 1<br>
+; NEVER-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP9]] to i64*<br>
+; NEVER-NEXT: store i64 0, i64* [[TMP11]], align 1<br>
; NEVER-NEXT: ret void<br>
;<br>
; RUNTIME-LABEL: @Simple(<br>
@@ -75,29 +73,26 @@ define void @Simple() uwtable sanitize_address {<br>
; RUNTIME-NEXT: store i64 ptrtoint (void ()* @Simple to i64), i64* [[TMP17]], align 8<br>
; RUNTIME-NEXT: [[TMP18:%.*]] = lshr i64 [[TMP10]], 3<br>
; RUNTIME-NEXT: [[TMP19:%.*]] = add i64 [[TMP18]], 2147450880<br>
-; RUNTIME-NEXT: [[TMP20:%.*]] = add i64 [[TMP19]], 0<br>
-; RUNTIME-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP20]] to i64*<br>
-; RUNTIME-NEXT: store i64 -868083113472691727, i64* [[TMP21]], align 1<br>
+; RUNTIME-NEXT: [[TMP20:%.*]] = inttoptr i64 [[TMP19]] to i64*<br>
+; RUNTIME-NEXT: store i64 -868083113472691727, i64* [[TMP20]], align 1<br>
; RUNTIME-NEXT: call void @Foo(i8* [[TMP12]])<br>
; RUNTIME-NEXT: store i64 1172321806, i64* [[TMP13]], align 8<br>
-; RUNTIME-NEXT: [[TMP22:%.*]] = icmp ne i64 [[TMP5]], 0<br>
-; RUNTIME-NEXT: br i1 [[TMP22]], label [[TMP23:%.*]], label [[TMP30:%.*]]<br>
-; RUNTIME: 23:<br>
-; RUNTIME-NEXT: [[TMP24:%.*]] = add i64 [[TMP19]], 0<br>
+; RUNTIME-NEXT: [[TMP21:%.*]] = icmp ne i64 [[TMP5]], 0<br>
+; RUNTIME-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP28:%.*]]<br>
+; RUNTIME: 22:<br>
+; RUNTIME-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP19]] to i64*<br>
+; RUNTIME-NEXT: store i64 -723401728380766731, i64* [[TMP23]], align 1<br>
+; RUNTIME-NEXT: [[TMP24:%.*]] = add i64 [[TMP5]], 56<br>
; RUNTIME-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP24]] to i64*<br>
-; RUNTIME-NEXT: store i64 -723401728380766731, i64* [[TMP25]], align 1<br>
-; RUNTIME-NEXT: [[TMP26:%.*]] = add i64 [[TMP5]], 56<br>
-; RUNTIME-NEXT: [[TMP27:%.*]] = inttoptr i64 [[TMP26]] to i64*<br>
-; RUNTIME-NEXT: [[TMP28:%.*]] = load i64, i64* [[TMP27]], align 8<br>
-; RUNTIME-NEXT: [[TMP29:%.*]] = inttoptr i64 [[TMP28]] to i8*<br>
-; RUNTIME-NEXT: store i8 0, i8* [[TMP29]], align 1<br>
-; RUNTIME-NEXT: br label [[TMP33:%.*]]<br>
+; RUNTIME-NEXT: [[TMP26:%.*]] = load i64, i64* [[TMP25]], align 8<br>
+; RUNTIME-NEXT: [[TMP27:%.*]] = inttoptr i64 [[TMP26]] to i8*<br>
+; RUNTIME-NEXT: store i8 0, i8* [[TMP27]], align 1<br>
+; RUNTIME-NEXT: br label [[TMP30:%.*]]<br>
+; RUNTIME: 28:<br>
+; RUNTIME-NEXT: [[TMP29:%.*]] = inttoptr i64 [[TMP19]] to i64*<br>
+; RUNTIME-NEXT: store i64 0, i64* [[TMP29]], align 1<br>
+; RUNTIME-NEXT: br label [[TMP30]]<br>
; RUNTIME: 30:<br>
-; RUNTIME-NEXT: [[TMP31:%.*]] = add i64 [[TMP19]], 0<br>
-; RUNTIME-NEXT: [[TMP32:%.*]] = inttoptr i64 [[TMP31]] to i64*<br>
-; RUNTIME-NEXT: store i64 0, i64* [[TMP32]], align 1<br>
-; RUNTIME-NEXT: br label [[TMP33]]<br>
-; RUNTIME: 33:<br>
; RUNTIME-NEXT: ret void<br>
;<br>
; ALWAYS-LABEL: @Simple(<br>
@@ -125,29 +120,26 @@ define void @Simple() uwtable sanitize_address {<br>
; ALWAYS-NEXT: store i64 ptrtoint (void ()* @Simple to i64), i64* [[TMP12]], align 8<br>
; ALWAYS-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP5]], 3<br>
; ALWAYS-NEXT: [[TMP14:%.*]] = add i64 [[TMP13]], 2147450880<br>
-; ALWAYS-NEXT: [[TMP15:%.*]] = add i64 [[TMP14]], 0<br>
-; ALWAYS-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP15]] to i64*<br>
-; ALWAYS-NEXT: store i64 -868083113472691727, i64* [[TMP16]], align 1<br>
+; ALWAYS-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to i64*<br>
+; ALWAYS-NEXT: store i64 -868083113472691727, i64* [[TMP15]], align 1<br>
; ALWAYS-NEXT: call void @Foo(i8* [[TMP7]])<br>
; ALWAYS-NEXT: store i64 1172321806, i64* [[TMP8]], align 8<br>
-; ALWAYS-NEXT: [[TMP17:%.*]] = icmp ne i64 [[TMP0]], 0<br>
-; ALWAYS-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP25:%.*]]<br>
-; ALWAYS: 18:<br>
-; ALWAYS-NEXT: [[TMP19:%.*]] = add i64 [[TMP14]], 0<br>
+; ALWAYS-NEXT: [[TMP16:%.*]] = icmp ne i64 [[TMP0]], 0<br>
+; ALWAYS-NEXT: br i1 [[TMP16]], label [[TMP17:%.*]], label [[TMP23:%.*]]<br>
+; ALWAYS: 17:<br>
+; ALWAYS-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP14]] to i64*<br>
+; ALWAYS-NEXT: store i64 -723401728380766731, i64* [[TMP18]], align 1<br>
+; ALWAYS-NEXT: [[TMP19:%.*]] = add i64 [[TMP0]], 56<br>
; ALWAYS-NEXT: [[TMP20:%.*]] = inttoptr i64 [[TMP19]] to i64*<br>
-; ALWAYS-NEXT: store i64 -723401728380766731, i64* [[TMP20]], align 1<br>
-; ALWAYS-NEXT: [[TMP21:%.*]] = add i64 [[TMP0]], 56<br>
-; ALWAYS-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP21]] to i64*<br>
-; ALWAYS-NEXT: [[TMP23:%.*]] = load i64, i64* [[TMP22]], align 8<br>
-; ALWAYS-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP23]] to i8*<br>
-; ALWAYS-NEXT: store i8 0, i8* [[TMP24]], align 1<br>
-; ALWAYS-NEXT: br label [[TMP28:%.*]]<br>
+; ALWAYS-NEXT: [[TMP21:%.*]] = load i64, i64* [[TMP20]], align 8<br>
+; ALWAYS-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP21]] to i8*<br>
+; ALWAYS-NEXT: store i8 0, i8* [[TMP22]], align 1<br>
+; ALWAYS-NEXT: br label [[TMP25:%.*]]<br>
+; ALWAYS: 23:<br>
+; ALWAYS-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP14]] to i64*<br>
+; ALWAYS-NEXT: store i64 0, i64* [[TMP24]], align 1<br>
+; ALWAYS-NEXT: br label [[TMP25]]<br>
; ALWAYS: 25:<br>
-; ALWAYS-NEXT: [[TMP26:%.*]] = add i64 [[TMP14]], 0<br>
-; ALWAYS-NEXT: [[TMP27:%.*]] = inttoptr i64 [[TMP26]] to i64*<br>
-; ALWAYS-NEXT: store i64 0, i64* [[TMP27]], align 1<br>
-; ALWAYS-NEXT: br label [[TMP28]]<br>
-; ALWAYS: 28:<br>
; ALWAYS-NEXT: ret void<br>
;<br>
entry:<br>
@@ -173,39 +165,37 @@ define void @Huge() uwtable sanitize_address {<br>
; CHECK-NEXT: store i64 ptrtoint (void ()* @Huge to i64), i64* [[TMP7]], align 8<br>
; CHECK-NEXT: [[TMP8:%.*]] = lshr i64 [[TMP0]], 3<br>
; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP8]], 2147450880<br>
-; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 0<br>
-; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to i32*<br>
-; CHECK-NEXT: store i32 -235802127, i32* [[TMP11]], align 1<br>
-; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP9]], 12504<br>
-; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to i64*<br>
-; CHECK-NEXT: store i64 -868082074056920077, i64* [[TMP13]], align 1<br>
-; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP9]], 12512<br>
-; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to i64*<br>
-; CHECK-NEXT: store i64 -868082074056920077, i64* [[TMP15]], align 1<br>
-; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[TMP9]], 12520<br>
-; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP16]] to i64*<br>
-; CHECK-NEXT: store i64 -868082074056920077, i64* [[TMP17]], align 1<br>
-; CHECK-NEXT: [[TMP18:%.*]] = add i64 [[TMP9]], 12528<br>
-; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP18]] to i64*<br>
-; CHECK-NEXT: store i64 -868082074056920077, i64* [[TMP19]], align 1<br>
+; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to i32*<br>
+; CHECK-NEXT: store i32 -235802127, i32* [[TMP10]], align 1<br>
+; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[TMP9]], 12504<br>
+; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to i64*<br>
+; CHECK-NEXT: store i64 -868082074056920077, i64* [[TMP12]], align 1<br>
+; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP9]], 12512<br>
+; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to i64*<br>
+; CHECK-NEXT: store i64 -868082074056920077, i64* [[TMP14]], align 1<br>
+; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[TMP9]], 12520<br>
+; CHECK-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP15]] to i64*<br>
+; CHECK-NEXT: store i64 -868082074056920077, i64* [[TMP16]], align 1<br>
+; CHECK-NEXT: [[TMP17:%.*]] = add i64 [[TMP9]], 12528<br>
+; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to i64*<br>
+; CHECK-NEXT: store i64 -868082074056920077, i64* [[TMP18]], align 1<br>
; CHECK-NEXT: [[XX:%.*]] = getelementptr inbounds [100000 x i8], [100000 x i8]* [[TMP2]], i64 0, i64 0<br>
; CHECK-NEXT: call void @Foo(i8* [[XX]])<br>
; CHECK-NEXT: store i64 1172321806, i64* [[TMP3]], align 8<br>
-; CHECK-NEXT: [[TMP20:%.*]] = add i64 [[TMP9]], 0<br>
-; CHECK-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP20]] to i32*<br>
-; CHECK-NEXT: store i32 0, i32* [[TMP21]], align 1<br>
-; CHECK-NEXT: [[TMP22:%.*]] = add i64 [[TMP9]], 12504<br>
+; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP9]] to i32*<br>
+; CHECK-NEXT: store i32 0, i32* [[TMP19]], align 1<br>
+; CHECK-NEXT: [[TMP20:%.*]] = add i64 [[TMP9]], 12504<br>
+; CHECK-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP20]] to i64*<br>
+; CHECK-NEXT: store i64 0, i64* [[TMP21]], align 1<br>
+; CHECK-NEXT: [[TMP22:%.*]] = add i64 [[TMP9]], 12512<br>
; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to i64*<br>
; CHECK-NEXT: store i64 0, i64* [[TMP23]], align 1<br>
-; CHECK-NEXT: [[TMP24:%.*]] = add i64 [[TMP9]], 12512<br>
+; CHECK-NEXT: [[TMP24:%.*]] = add i64 [[TMP9]], 12520<br>
; CHECK-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP24]] to i64*<br>
; CHECK-NEXT: store i64 0, i64* [[TMP25]], align 1<br>
-; CHECK-NEXT: [[TMP26:%.*]] = add i64 [[TMP9]], 12520<br>
+; CHECK-NEXT: [[TMP26:%.*]] = add i64 [[TMP9]], 12528<br>
; CHECK-NEXT: [[TMP27:%.*]] = inttoptr i64 [[TMP26]] to i64*<br>
; CHECK-NEXT: store i64 0, i64* [[TMP27]], align 1<br>
-; CHECK-NEXT: [[TMP28:%.*]] = add i64 [[TMP9]], 12528<br>
-; CHECK-NEXT: [[TMP29:%.*]] = inttoptr i64 [[TMP28]] to i64*<br>
-; CHECK-NEXT: store i64 0, i64* [[TMP29]], align 1<br>
; CHECK-NEXT: ret void<br>
;<br>
entry:<br>
<br>
diff --git a/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime-be.ll b/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime-be.ll<br>
index 91b0f53d4c6d4..d1423a868ca8b 100644<br>
--- a/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime-be.ll<br>
+++ b/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime-be.ll<br>
@@ -23,8 +23,7 @@ entry:<br>
; CHECK: [[SHADOW_BASE:%[0-9]+]] = add i64 %{{[0-9]+}}, 17592186044416<br>
<br>
; F1F1F1F1<br>
- ; ENTRY-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0<br>
- ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]*<br>
+ ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[SHADOW_BASE]] to [[TYPE:i32]]*<br>
; ENTRY-NEXT: store [[TYPE]] -235802127, [[TYPE]]* [[PTR]], align 1<br>
<br>
; 02F2F2F2F2F2F2F2<br>
@@ -53,8 +52,7 @@ entry:<br>
; ENTRY-NEXT: store [[TYPE]] -13, [[TYPE]]* [[PTR]], align 1<br>
<br>
; F1F1F1F1<br>
- ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0<br>
- ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]*<br>
+ ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[SHADOW_BASE]] to [[TYPE:i32]]*<br>
; ENTRY-UAS-NEXT: store [[TYPE]] -235802127, [[TYPE]]* [[PTR]], align 1<br>
<br>
; F8F8F8...<br>
@@ -161,16 +159,14 @@ entry:<br>
<br>
; CHECK: {{^[0-9]+}}:<br>
<br>
- ; CHECK-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0<br>
- ; CHECK-NEXT: call void @__asan_set_shadow_f5(i64 [[OFFSET]], i64 128)<br>
+ ; CHECK-NEXT: call void @__asan_set_shadow_f5(i64 [[SHADOW_BASE]], i64 128)<br>
<br>
; CHECK-NOT: add i64 [[SHADOW_BASE]]<br>
<br>
; CHECK: {{^[0-9]+}}:<br>
<br>
; 00000000<br>
- ; EXIT-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0<br>
- ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]*<br>
+ ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[SHADOW_BASE]] to [[TYPE:i32]]*<br>
; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1<br>
<br>
; 0000000000000000<br>
@@ -199,8 +195,7 @@ entry:<br>
; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1<br>
<br>
; 0000...<br>
- ; EXIT-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0<br>
- ; EXIT-UAS-NEXT: call void @__asan_set_shadow_00(i64 [[OFFSET]], i64 116)<br>
+ ; EXIT-UAS-NEXT: call void @__asan_set_shadow_00(i64 [[SHADOW_BASE]], i64 116)<br>
<br>
; CHECK-NOT: add i64 [[SHADOW_BASE]]<br>
<br>
<br>
diff --git a/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime.ll b/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime.ll<br>
index 6604f5f924dae..a970554e469cb 100644<br>
--- a/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime.ll<br>
+++ b/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime.ll<br>
@@ -23,8 +23,7 @@ entry:<br>
; CHECK: [[SHADOW_BASE:%[0-9]+]] = add i64 %{{[0-9]+}}, 2147450880<br>
<br>
; F1F1F1F1<br>
- ; ENTRY-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0<br>
- ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]*<br>
+ ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[SHADOW_BASE]] to [[TYPE:i32]]*<br>
; ENTRY-NEXT: store [[TYPE]] -235802127, [[TYPE]]* [[PTR]], align 1<br>
<br>
; 02F2F2F2F2F2F2F2<br>
@@ -53,8 +52,7 @@ entry:<br>
; ENTRY-NEXT: store [[TYPE]] -13, [[TYPE]]* [[PTR]], align 1<br>
<br>
; F1F1F1F1<br>
- ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0<br>
- ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]*<br>
+ ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[SHADOW_BASE]] to [[TYPE:i32]]*<br>
; ENTRY-UAS-NEXT: store [[TYPE]] -235802127, [[TYPE]]* [[PTR]], align 1<br>
<br>
; F8F8F8...<br>
@@ -161,16 +159,14 @@ entry:<br>
<br>
; CHECK: {{^[0-9]+}}:<br>
<br>
- ; CHECK-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0<br>
- ; CHECK-NEXT: call void @__asan_set_shadow_f5(i64 [[OFFSET]], i64 128)<br>
+ ; CHECK-NEXT: call void @__asan_set_shadow_f5(i64 [[SHADOW_BASE]], i64 128)<br>
<br>
; CHECK-NOT: add i64 [[SHADOW_BASE]]<br>
<br>
; CHECK: {{^[0-9]+}}:<br>
<br>
; 00000000<br>
- ; EXIT-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0<br>
- ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]*<br>
+ ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[SHADOW_BASE]] to [[TYPE:i32]]*<br>
; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1<br>
<br>
; 0000000000000000<br>
@@ -199,8 +195,7 @@ entry:<br>
; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1<br>
<br>
; 0000...<br>
- ; EXIT-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0<br>
- ; EXIT-UAS-NEXT: call void @__asan_set_shadow_00(i64 [[OFFSET]], i64 116)<br>
+ ; EXIT-UAS-NEXT: call void @__asan_set_shadow_00(i64 [[SHADOW_BASE]], i64 116)<br>
<br>
; CHECK-NOT: add i64 [[SHADOW_BASE]]<br>
<br>
<br>
diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/basic.ll b/llvm/test/Instrumentation/HWAddressSanitizer/basic.ll<br>
index d4e4e11865630..473a69783e17e 100644<br>
--- a/llvm/test/Instrumentation/HWAddressSanitizer/basic.ll<br>
+++ b/llvm/test/Instrumentation/HWAddressSanitizer/basic.ll<br>
@@ -35,8 +35,7 @@ define i8 @test_load8(i8* %a) sanitize_hwaddress {<br>
; RECOVER: [[SHORT]]:<br>
; RECOVER: %[[LOWBITS:[^ ]*]] = and i64 %[[A]], 15<br>
; RECOVER: %[[LOWBITS_I8:[^ ]*]] = trunc i64 %[[LOWBITS]] to i8<br>
-; RECOVER: %[[LAST:[^ ]*]] = add i8 %[[LOWBITS_I8]], 0<br>
-; RECOVER: %[[OOB:[^ ]*]] = icmp uge i8 %[[LAST]], %[[MEMTAG]]<br>
+; RECOVER: %[[OOB:[^ ]*]] = icmp uge i8 %[[LOWBITS_I8]], %[[MEMTAG]]<br>
; RECOVER: br i1 %[[OOB]], label %[[FAIL]], label %[[INBOUNDS:[0-9]*]], !prof {{.*}}<br>
<br>
; RECOVER: [[INBOUNDS]]:<br>
<br>
diff --git a/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll b/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll<br>
index c87cce471a849..a27311f95bfde 100644<br>
--- a/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll<br>
+++ b/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll<br>
@@ -18,10 +18,9 @@ define i32 @foo(i32 %guard, ...) {<br>
<br>
; CHECK-LABEL: @foo<br>
; CHECK: [[A:%.*]] = load {{.*}} @__msan_va_arg_overflow_size_tls<br>
-; CHECK: [[B:%.*]] = add i64 [[A]], 0<br>
-; CHECK: [[C:%.*]] = alloca {{.*}} [[B]]<br>
+; CHECK: [[C:%.*]] = alloca {{.*}} [[A]]<br>
<br>
-; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[C]], i8* align 8 bitcast ({{.*}} @__msan_va_arg_tls to i8*), i64 [[B]], i1 false)<br>
+; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[C]], i8* align 8 bitcast ({{.*}} @__msan_va_arg_tls to i8*), i64 [[A]], i1 false)<br>
<br>
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1<br>
declare void @llvm.va_start(i8*) #2<br>
<br>
diff --git a/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll b/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll<br>
index 31efc7aa5eab4..f7dd2aef525ed 100644<br>
--- a/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll<br>
+++ b/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll<br>
@@ -18,10 +18,9 @@ define i32 @foo(i32 %guard, ...) {<br>
<br>
; CHECK-LABEL: @foo<br>
; CHECK: [[A:%.*]] = load {{.*}} @__msan_va_arg_overflow_size_tls<br>
-; CHECK: [[B:%.*]] = add i64 [[A]], 0<br>
-; CHECK: [[C:%.*]] = alloca {{.*}} [[B]]<br>
+; CHECK: [[C:%.*]] = alloca {{.*}} [[A]]<br>
<br>
-; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[C]], i8* align 8 bitcast ({{.*}} @__msan_va_arg_tls to i8*), i64 [[B]], i1 false)<br>
+; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[C]], i8* align 8 bitcast ({{.*}} @__msan_va_arg_tls to i8*), i64 [[A]], i1 false)<br>
<br>
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1<br>
declare void @llvm.va_start(i8*) #2<br>
<br>
diff --git a/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll b/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll<br>
index 2dc2bde7b835e..b45a4fc32352a 100644<br>
--- a/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll<br>
+++ b/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll<br>
@@ -18,10 +18,9 @@ define i32 @foo(i32 %guard, ...) {<br>
<br>
; CHECK-LABEL: @foo<br>
; CHECK: [[A:%.*]] = load {{.*}} @__msan_va_arg_overflow_size_tls<br>
-; CHECK: [[B:%.*]] = add i64 [[A]], 0<br>
-; CHECK: [[C:%.*]] = alloca {{.*}} [[B]]<br>
+; CHECK: [[C:%.*]] = alloca {{.*}} [[A]]<br>
<br>
-; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[C]], i8* align 8 bitcast ({{.*}} @__msan_va_arg_tls to i8*), i64 [[B]], i1 false)<br>
+; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[C]], i8* align 8 bitcast ({{.*}} @__msan_va_arg_tls to i8*), i64 [[A]], i1 false)<br>
<br>
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1<br>
declare void @llvm.va_start(i8*) #2<br>
<br>
diff --git a/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll b/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll<br>
index 4db0785e8dd2e..b7515e040ab17 100644<br>
--- a/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll<br>
+++ b/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll<br>
@@ -18,10 +18,9 @@ define i32 @foo(i32 %guard, ...) {<br>
<br>
; CHECK-LABEL: @foo<br>
; CHECK: [[A:%.*]] = load {{.*}} @__msan_va_arg_overflow_size_tls<br>
-; CHECK: [[B:%.*]] = add i64 [[A]], 0<br>
-; CHECK: [[C:%.*]] = alloca {{.*}} [[B]]<br>
+; CHECK: [[C:%.*]] = alloca {{.*}} [[A]]<br>
<br>
-; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[C]], i8* align 8 bitcast ({{.*}} @__msan_va_arg_tls to i8*), i64 [[B]], i1 false)<br>
+; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[C]], i8* align 8 bitcast ({{.*}} @__msan_va_arg_tls to i8*), i64 [[A]], i1 false)<br>
<br>
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1<br>
declare void @llvm.va_start(i8*) #2<br>
<br>
diff --git a/llvm/test/Transforms/LoopDistribute/scev-inserted-runtime-check.ll b/llvm/test/Transforms/LoopDistribute/scev-inserted-runtime-check.ll<br>
index 077d604ced395..301f24813255b 100644<br>
--- a/llvm/test/Transforms/LoopDistribute/scev-inserted-runtime-check.ll<br>
+++ b/llvm/test/Transforms/LoopDistribute/scev-inserted-runtime-check.ll<br>
@@ -17,24 +17,23 @@ define void @f(i32* noalias %a, i32* noalias %b, i32* noalias %c, i32* noalias %<br>
; CHECK-NEXT: [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP1]])<br>
; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0<br>
; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1<br>
-; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[MUL_RESULT]], 0<br>
-; CHECK-NEXT: [[TMP3:%.*]] = sub i32 0, [[MUL_RESULT]]<br>
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt i32 [[TMP3]], 0<br>
-; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP2]], 0<br>
-; CHECK-NEXT: [[TMP6:%.*]] = icmp ugt i64 [[TMP0]], 4294967295<br>
-; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]<br>
-; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW]]<br>
+; CHECK-NEXT: [[TMP2:%.*]] = sub i32 0, [[MUL_RESULT]]<br>
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i32 [[TMP2]], 0<br>
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[MUL_RESULT]], 0<br>
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ugt i64 [[TMP0]], 4294967295<br>
+; CHECK-NEXT: [[TMP6:%.*]] = or i1 [[TMP4]], [[TMP5]]<br>
+; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP6]], [[MUL_OVERFLOW]]<br>
; CHECK-NEXT: [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 8, i64 [[TMP0]])<br>
; CHECK-NEXT: [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0<br>
; CHECK-NEXT: [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1<br>
-; CHECK-NEXT: [[TMP9:%.*]] = sub i64 0, [[MUL_RESULT3]]<br>
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, i8* [[A5]], i64 [[MUL_RESULT3]]<br>
-; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, i8* [[A5]], i64 [[TMP9]]<br>
-; CHECK-NEXT: [[TMP12:%.*]] = icmp ugt i8* [[TMP11]], [[A5]]<br>
-; CHECK-NEXT: [[TMP13:%.*]] = icmp ult i8* [[TMP10]], [[A5]]<br>
-; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP13]], [[MUL_OVERFLOW4]]<br>
-; CHECK-NEXT: [[TMP15:%.*]] = or i1 [[TMP8]], [[TMP14]]<br>
-; CHECK-NEXT: br i1 [[TMP15]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH_LDIST1:%.*]]<br>
+; CHECK-NEXT: [[TMP8:%.*]] = sub i64 0, [[MUL_RESULT3]]<br>
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, i8* [[A5]], i64 [[MUL_RESULT3]]<br>
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, i8* [[A5]], i64 [[TMP8]]<br>
+; CHECK-NEXT: [[TMP11:%.*]] = icmp ugt i8* [[TMP10]], [[A5]]<br>
+; CHECK-NEXT: [[TMP12:%.*]] = icmp ult i8* [[TMP9]], [[A5]]<br>
+; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP12]], [[MUL_OVERFLOW4]]<br>
+; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP7]], [[TMP13]]<br>
+; CHECK-NEXT: br i1 [[TMP14]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH_LDIST1:%.*]]<br>
; CHECK: for.body.ph.lver.orig:<br>
; CHECK-NEXT: br label [[FOR_BODY_LVER_ORIG:%.*]]<br>
; CHECK: for.body.lver.orig:<br>
@@ -163,24 +162,23 @@ define void @f_with_offset(i32* noalias %b, i32* noalias %c, i32* noalias %d, i3<br>
; CHECK-NEXT: [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP1]])<br>
; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0<br>
; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1<br>
-; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[MUL_RESULT]], 0<br>
-; CHECK-NEXT: [[TMP3:%.*]] = sub i32 0, [[MUL_RESULT]]<br>
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt i32 [[TMP3]], 0<br>
-; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP2]], 0<br>
-; CHECK-NEXT: [[TMP6:%.*]] = icmp ugt i64 [[TMP0]], 4294967295<br>
-; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]<br>
-; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW]]<br>
+; CHECK-NEXT: [[TMP2:%.*]] = sub i32 0, [[MUL_RESULT]]<br>
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i32 [[TMP2]], 0<br>
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[MUL_RESULT]], 0<br>
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ugt i64 [[TMP0]], 4294967295<br>
+; CHECK-NEXT: [[TMP6:%.*]] = or i1 [[TMP4]], [[TMP5]]<br>
+; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP6]], [[MUL_OVERFLOW]]<br>
; CHECK-NEXT: [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 8, i64 [[TMP0]])<br>
; CHECK-NEXT: [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0<br>
; CHECK-NEXT: [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1<br>
-; CHECK-NEXT: [[TMP9:%.*]] = sub i64 0, [[MUL_RESULT3]]<br>
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, i8* bitcast (i32* getelementptr inbounds ([8192 x i32], [8192 x i32]* @global_a, i64 0, i64 42) to i8*), i64 [[MUL_RESULT3]]<br>
-; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, i8* bitcast (i32* getelementptr inbounds ([8192 x i32], [8192 x i32]* @global_a, i64 0, i64 42) to i8*), i64 [[TMP9]]<br>
-; CHECK-NEXT: [[TMP12:%.*]] = icmp ugt i8* [[TMP11]], bitcast (i32* getelementptr inbounds ([8192 x i32], [8192 x i32]* @global_a, i64 0, i64 42) to i8*)<br>
-; CHECK-NEXT: [[TMP13:%.*]] = icmp ult i8* [[TMP10]], bitcast (i32* getelementptr inbounds ([8192 x i32], [8192 x i32]* @global_a, i64 0, i64 42) to i8*)<br>
-; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP13]], [[MUL_OVERFLOW4]]<br>
-; CHECK-NEXT: [[TMP15:%.*]] = or i1 [[TMP8]], [[TMP14]]<br>
-; CHECK-NEXT: br i1 [[TMP15]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH_LDIST1:%.*]]<br>
+; CHECK-NEXT: [[TMP8:%.*]] = sub i64 0, [[MUL_RESULT3]]<br>
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, i8* bitcast (i32* getelementptr inbounds ([8192 x i32], [8192 x i32]* @global_a, i64 0, i64 42) to i8*), i64 [[MUL_RESULT3]]<br>
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, i8* bitcast (i32* getelementptr inbounds ([8192 x i32], [8192 x i32]* @global_a, i64 0, i64 42) to i8*), i64 [[TMP8]]<br>
+; CHECK-NEXT: [[TMP11:%.*]] = icmp ugt i8* [[TMP10]], bitcast (i32* getelementptr inbounds ([8192 x i32], [8192 x i32]* @global_a, i64 0, i64 42) to i8*)<br>
+; CHECK-NEXT: [[TMP12:%.*]] = icmp ult i8* [[TMP9]], bitcast (i32* getelementptr inbounds ([8192 x i32], [8192 x i32]* @global_a, i64 0, i64 42) to i8*)<br>
+; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP12]], [[MUL_OVERFLOW4]]<br>
+; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP7]], [[TMP13]]<br>
+; CHECK-NEXT: br i1 [[TMP14]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH_LDIST1:%.*]]<br>
; CHECK: for.body.ph.lver.orig:<br>
; CHECK-NEXT: br label [[FOR_BODY_LVER_ORIG:%.*]]<br>
; CHECK: for.body.lver.orig:<br>
<br>
diff --git a/llvm/test/Transforms/LoopIdiom/X86/arithmetic-right-shift-until-zero.ll b/llvm/test/Transforms/LoopIdiom/X86/arithmetic-right-shift-until-zero.ll<br>
index 9079773ca1a8d..d42743ea622b7 100644<br>
--- a/llvm/test/Transforms/LoopIdiom/X86/arithmetic-right-shift-until-zero.ll<br>
+++ b/llvm/test/Transforms/LoopIdiom/X86/arithmetic-right-shift-until-zero.ll<br>
@@ -327,8 +327,7 @@ define i8 @p6(i8 %val, i8 %start) mustprogress {<br>
; CHECK-NEXT: entry:<br>
; CHECK-NEXT: [[VAL_NUMLEADINGZEROS:%.*]] = call i8 @llvm.ctlz.i8(i8 [[VAL:%.*]], i1 false)<br>
; CHECK-NEXT: [[VAL_NUMACTIVEBITS:%.*]] = sub nuw nsw i8 8, [[VAL_NUMLEADINGZEROS]]<br>
-; CHECK-NEXT: [[VAL_NUMACTIVEBITS_OFFSET:%.*]] = add nuw nsw i8 [[VAL_NUMACTIVEBITS]], 0<br>
-; CHECK-NEXT: [[IV_FINAL:%.*]] = call i8 @llvm.smax.i8(i8 [[VAL_NUMACTIVEBITS_OFFSET]], i8 [[START:%.*]])<br>
+; CHECK-NEXT: [[IV_FINAL:%.*]] = call i8 @llvm.smax.i8(i8 [[VAL_NUMACTIVEBITS]], i8 [[START:%.*]])<br>
; CHECK-NEXT: [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub nuw nsw i8 [[IV_FINAL]], [[START]]<br>
; CHECK-NEXT: [[LOOP_TRIPCOUNT:%.*]] = add nuw nsw i8 [[LOOP_BACKEDGETAKENCOUNT]], 1<br>
; CHECK-NEXT: br label [[LOOP:%.*]]<br>
@@ -1263,8 +1262,7 @@ define i1 @t24_nooffset_i1(i1 %val, i1 %start) mustprogress {<br>
; CHECK-NEXT: entry:<br>
; CHECK-NEXT: [[VAL_NUMLEADINGZEROS:%.*]] = call i1 @llvm.ctlz.i1(i1 [[VAL:%.*]], i1 false)<br>
; CHECK-NEXT: [[VAL_NUMACTIVEBITS:%.*]] = sub nuw nsw i1 true, [[VAL_NUMLEADINGZEROS]]<br>
-; CHECK-NEXT: [[VAL_NUMACTIVEBITS_OFFSET:%.*]] = add nuw nsw i1 [[VAL_NUMACTIVEBITS]], false<br>
-; CHECK-NEXT: [[IV_FINAL:%.*]] = call i1 @llvm.smax.i1(i1 [[VAL_NUMACTIVEBITS_OFFSET]], i1 [[START:%.*]])<br>
+; CHECK-NEXT: [[IV_FINAL:%.*]] = call i1 @llvm.smax.i1(i1 [[VAL_NUMACTIVEBITS]], i1 [[START:%.*]])<br>
; CHECK-NEXT: [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub nuw nsw i1 [[IV_FINAL]], [[START]]<br>
; CHECK-NEXT: [[LOOP_TRIPCOUNT:%.*]] = add nuw nsw i1 [[LOOP_BACKEDGETAKENCOUNT]], true<br>
; CHECK-NEXT: br label [[LOOP:%.*]]<br>
@@ -1313,8 +1311,7 @@ define i2 @t25_nooffset_i2(i2 %val, i2 %start) mustprogress {<br>
; CHECK-NEXT: entry:<br>
; CHECK-NEXT: [[VAL_NUMLEADINGZEROS:%.*]] = call i2 @llvm.ctlz.i2(i2 [[VAL:%.*]], i1 false)<br>
; CHECK-NEXT: [[VAL_NUMACTIVEBITS:%.*]] = sub nuw i2 -2, [[VAL_NUMLEADINGZEROS]]<br>
-; CHECK-NEXT: [[VAL_NUMACTIVEBITS_OFFSET:%.*]] = add nuw nsw i2 [[VAL_NUMACTIVEBITS]], 0<br>
-; CHECK-NEXT: [[IV_FINAL:%.*]] = call i2 @llvm.smax.i2(i2 [[VAL_NUMACTIVEBITS_OFFSET]], i2 [[START:%.*]])<br>
+; CHECK-NEXT: [[IV_FINAL:%.*]] = call i2 @llvm.smax.i2(i2 [[VAL_NUMACTIVEBITS]], i2 [[START:%.*]])<br>
; CHECK-NEXT: [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub nuw nsw i2 [[IV_FINAL]], [[START]]<br>
; CHECK-NEXT: [[LOOP_TRIPCOUNT:%.*]] = add nuw i2 [[LOOP_BACKEDGETAKENCOUNT]], 1<br>
; CHECK-NEXT: br label [[LOOP:%.*]]<br>
@@ -1363,8 +1360,7 @@ define i3 @t26_nooffset_i3(i3 %val, i3 %start) mustprogress {<br>
; CHECK-NEXT: entry:<br>
; CHECK-NEXT: [[VAL_NUMLEADINGZEROS:%.*]] = call i3 @llvm.ctlz.i3(i3 [[VAL:%.*]], i1 false)<br>
; CHECK-NEXT: [[VAL_NUMACTIVEBITS:%.*]] = sub nuw nsw i3 3, [[VAL_NUMLEADINGZEROS]]<br>
-; CHECK-NEXT: [[VAL_NUMACTIVEBITS_OFFSET:%.*]] = add nuw nsw i3 [[VAL_NUMACTIVEBITS]], 0<br>
-; CHECK-NEXT: [[IV_FINAL:%.*]] = call i3 @llvm.smax.i3(i3 [[VAL_NUMACTIVEBITS_OFFSET]], i3 [[START:%.*]])<br>
+; CHECK-NEXT: [[IV_FINAL:%.*]] = call i3 @llvm.smax.i3(i3 [[VAL_NUMACTIVEBITS]], i3 [[START:%.*]])<br>
; CHECK-NEXT: [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub nuw nsw i3 [[IV_FINAL]], [[START]]<br>
; CHECK-NEXT: [[LOOP_TRIPCOUNT:%.*]] = add nuw nsw i3 [[LOOP_BACKEDGETAKENCOUNT]], 1<br>
; CHECK-NEXT: br label [[LOOP:%.*]]<br>
<br>
diff --git a/llvm/test/Transforms/LoopIdiom/X86/left-shift-until-zero.ll b/llvm/test/Transforms/LoopIdiom/X86/left-shift-until-zero.ll<br>
index d32fd50f29921..7b156442b59c5 100644<br>
--- a/llvm/test/Transforms/LoopIdiom/X86/left-shift-until-zero.ll<br>
+++ b/llvm/test/Transforms/LoopIdiom/X86/left-shift-until-zero.ll<br>
@@ -327,8 +327,7 @@ define i8 @p6(i8 %val, i8 %start) {<br>
; CHECK-NEXT: entry:<br>
; CHECK-NEXT: [[VAL_NUMLEADINGZEROS:%.*]] = call i8 @llvm.cttz.i8(i8 [[VAL:%.*]], i1 false)<br>
; CHECK-NEXT: [[VAL_NUMACTIVEBITS:%.*]] = sub nuw nsw i8 8, [[VAL_NUMLEADINGZEROS]]<br>
-; CHECK-NEXT: [[VAL_NUMACTIVEBITS_OFFSET:%.*]] = add nuw nsw i8 [[VAL_NUMACTIVEBITS]], 0<br>
-; CHECK-NEXT: [[IV_FINAL:%.*]] = call i8 @llvm.smax.i8(i8 [[VAL_NUMACTIVEBITS_OFFSET]], i8 [[START:%.*]])<br>
+; CHECK-NEXT: [[IV_FINAL:%.*]] = call i8 @llvm.smax.i8(i8 [[VAL_NUMACTIVEBITS]], i8 [[START:%.*]])<br>
; CHECK-NEXT: [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub nuw nsw i8 [[IV_FINAL]], [[START]]<br>
; CHECK-NEXT: [[LOOP_TRIPCOUNT:%.*]] = add nuw nsw i8 [[LOOP_BACKEDGETAKENCOUNT]], 1<br>
; CHECK-NEXT: br label [[LOOP:%.*]]<br>
@@ -1263,8 +1262,7 @@ define i1 @t24_nooffset_i1(i1 %val, i1 %start) {<br>
; CHECK-NEXT: entry:<br>
; CHECK-NEXT: [[VAL_NUMLEADINGZEROS:%.*]] = call i1 @llvm.cttz.i1(i1 [[VAL:%.*]], i1 false)<br>
; CHECK-NEXT: [[VAL_NUMACTIVEBITS:%.*]] = sub nuw nsw i1 true, [[VAL_NUMLEADINGZEROS]]<br>
-; CHECK-NEXT: [[VAL_NUMACTIVEBITS_OFFSET:%.*]] = add nuw nsw i1 [[VAL_NUMACTIVEBITS]], false<br>
-; CHECK-NEXT: [[IV_FINAL:%.*]] = call i1 @llvm.smax.i1(i1 [[VAL_NUMACTIVEBITS_OFFSET]], i1 [[START:%.*]])<br>
+; CHECK-NEXT: [[IV_FINAL:%.*]] = call i1 @llvm.smax.i1(i1 [[VAL_NUMACTIVEBITS]], i1 [[START:%.*]])<br>
; CHECK-NEXT: [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub nuw nsw i1 [[IV_FINAL]], [[START]]<br>
; CHECK-NEXT: [[LOOP_TRIPCOUNT:%.*]] = add nuw nsw i1 [[LOOP_BACKEDGETAKENCOUNT]], true<br>
; CHECK-NEXT: br label [[LOOP:%.*]]<br>
@@ -1313,8 +1311,7 @@ define i2 @t25_nooffset_i2(i2 %val, i2 %start) {<br>
; CHECK-NEXT: entry:<br>
; CHECK-NEXT: [[VAL_NUMLEADINGZEROS:%.*]] = call i2 @llvm.cttz.i2(i2 [[VAL:%.*]], i1 false)<br>
; CHECK-NEXT: [[VAL_NUMACTIVEBITS:%.*]] = sub nuw i2 -2, [[VAL_NUMLEADINGZEROS]]<br>
-; CHECK-NEXT: [[VAL_NUMACTIVEBITS_OFFSET:%.*]] = add nuw nsw i2 [[VAL_NUMACTIVEBITS]], 0<br>
-; CHECK-NEXT: [[IV_FINAL:%.*]] = call i2 @llvm.smax.i2(i2 [[VAL_NUMACTIVEBITS_OFFSET]], i2 [[START:%.*]])<br>
+; CHECK-NEXT: [[IV_FINAL:%.*]] = call i2 @llvm.smax.i2(i2 [[VAL_NUMACTIVEBITS]], i2 [[START:%.*]])<br>
; CHECK-NEXT: [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub nuw nsw i2 [[IV_FINAL]], [[START]]<br>
; CHECK-NEXT: [[LOOP_TRIPCOUNT:%.*]] = add nuw i2 [[LOOP_BACKEDGETAKENCOUNT]], 1<br>
; CHECK-NEXT: br label [[LOOP:%.*]]<br>
@@ -1363,8 +1360,7 @@ define i3 @t26_nooffset_i3(i3 %val, i3 %start) {<br>
; CHECK-NEXT: entry:<br>
; CHECK-NEXT: [[VAL_NUMLEADINGZEROS:%.*]] = call i3 @llvm.cttz.i3(i3 [[VAL:%.*]], i1 false)<br>
; CHECK-NEXT: [[VAL_NUMACTIVEBITS:%.*]] = sub nuw nsw i3 3, [[VAL_NUMLEADINGZEROS]]<br>
-; CHECK-NEXT: [[VAL_NUMACTIVEBITS_OFFSET:%.*]] = add nuw nsw i3 [[VAL_NUMACTIVEBITS]], 0<br>
-; CHECK-NEXT: [[IV_FINAL:%.*]] = call i3 @llvm.smax.i3(i3 [[VAL_NUMACTIVEBITS_OFFSET]], i3 [[START:%.*]])<br>
+; CHECK-NEXT: [[IV_FINAL:%.*]] = call i3 @llvm.smax.i3(i3 [[VAL_NUMACTIVEBITS]], i3 [[START:%.*]])<br>
; CHECK-NEXT: [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub nuw nsw i3 [[IV_FINAL]], [[START]]<br>
; CHECK-NEXT: [[LOOP_TRIPCOUNT:%.*]] = add nuw nsw i3 [[LOOP_BACKEDGETAKENCOUNT]], 1<br>
; CHECK-NEXT: br label [[LOOP:%.*]]<br>
<br>
diff --git a/llvm/test/Transforms/LoopIdiom/X86/logical-right-shift-until-zero.ll b/llvm/test/Transforms/LoopIdiom/X86/logical-right-shift-until-zero.ll<br>
index a851ed5e38562..0c3de8754048f 100644<br>
--- a/llvm/test/Transforms/LoopIdiom/X86/logical-right-shift-until-zero.ll<br>
+++ b/llvm/test/Transforms/LoopIdiom/X86/logical-right-shift-until-zero.ll<br>
@@ -327,8 +327,7 @@ define i8 @p6(i8 %val, i8 %start) {<br>
; CHECK-NEXT: entry:<br>
; CHECK-NEXT: [[VAL_NUMLEADINGZEROS:%.*]] = call i8 @llvm.ctlz.i8(i8 [[VAL:%.*]], i1 false)<br>
; CHECK-NEXT: [[VAL_NUMACTIVEBITS:%.*]] = sub nuw nsw i8 8, [[VAL_NUMLEADINGZEROS]]<br>
-; CHECK-NEXT: [[VAL_NUMACTIVEBITS_OFFSET:%.*]] = add nuw nsw i8 [[VAL_NUMACTIVEBITS]], 0<br>
-; CHECK-NEXT: [[IV_FINAL:%.*]] = call i8 @llvm.smax.i8(i8 [[VAL_NUMACTIVEBITS_OFFSET]], i8 [[START:%.*]])<br>
+; CHECK-NEXT: [[IV_FINAL:%.*]] = call i8 @llvm.smax.i8(i8 [[VAL_NUMACTIVEBITS]], i8 [[START:%.*]])<br>
; CHECK-NEXT: [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub nuw nsw i8 [[IV_FINAL]], [[START]]<br>
; CHECK-NEXT: [[LOOP_TRIPCOUNT:%.*]] = add nuw nsw i8 [[LOOP_BACKEDGETAKENCOUNT]], 1<br>
; CHECK-NEXT: br label [[LOOP:%.*]]<br>
@@ -1263,8 +1262,7 @@ define i1 @t24_nooffset_i1(i1 %val, i1 %start) {<br>
; CHECK-NEXT: entry:<br>
; CHECK-NEXT: [[VAL_NUMLEADINGZEROS:%.*]] = call i1 @llvm.ctlz.i1(i1 [[VAL:%.*]], i1 false)<br>
; CHECK-NEXT: [[VAL_NUMACTIVEBITS:%.*]] = sub nuw nsw i1 true, [[VAL_NUMLEADINGZEROS]]<br>
-; CHECK-NEXT: [[VAL_NUMACTIVEBITS_OFFSET:%.*]] = add nuw nsw i1 [[VAL_NUMACTIVEBITS]], false<br>
-; CHECK-NEXT: [[IV_FINAL:%.*]] = call i1 @llvm.smax.i1(i1 [[VAL_NUMACTIVEBITS_OFFSET]], i1 [[START:%.*]])<br>
+; CHECK-NEXT: [[IV_FINAL:%.*]] = call i1 @llvm.smax.i1(i1 [[VAL_NUMACTIVEBITS]], i1 [[START:%.*]])<br>
; CHECK-NEXT: [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub nuw nsw i1 [[IV_FINAL]], [[START]]<br>
; CHECK-NEXT: [[LOOP_TRIPCOUNT:%.*]] = add nuw nsw i1 [[LOOP_BACKEDGETAKENCOUNT]], true<br>
; CHECK-NEXT: br label [[LOOP:%.*]]<br>
@@ -1313,8 +1311,7 @@ define i2 @t25_nooffset_i2(i2 %val, i2 %start) {<br>
; CHECK-NEXT: entry:<br>
; CHECK-NEXT: [[VAL_NUMLEADINGZEROS:%.*]] = call i2 @llvm.ctlz.i2(i2 [[VAL:%.*]], i1 false)<br>
; CHECK-NEXT: [[VAL_NUMACTIVEBITS:%.*]] = sub nuw i2 -2, [[VAL_NUMLEADINGZEROS]]<br>
-; CHECK-NEXT: [[VAL_NUMACTIVEBITS_OFFSET:%.*]] = add nuw nsw i2 [[VAL_NUMACTIVEBITS]], 0<br>
-; CHECK-NEXT: [[IV_FINAL:%.*]] = call i2 @llvm.smax.i2(i2 [[VAL_NUMACTIVEBITS_OFFSET]], i2 [[START:%.*]])<br>
+; CHECK-NEXT: [[IV_FINAL:%.*]] = call i2 @llvm.smax.i2(i2 [[VAL_NUMACTIVEBITS]], i2 [[START:%.*]])<br>
; CHECK-NEXT: [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub nuw nsw i2 [[IV_FINAL]], [[START]]<br>
; CHECK-NEXT: [[LOOP_TRIPCOUNT:%.*]] = add nuw i2 [[LOOP_BACKEDGETAKENCOUNT]], 1<br>
; CHECK-NEXT: br label [[LOOP:%.*]]<br>
@@ -1363,8 +1360,7 @@ define i3 @t26_nooffset_i3(i3 %val, i3 %start) {<br>
; CHECK-NEXT: entry:<br>
; CHECK-NEXT: [[VAL_NUMLEADINGZEROS:%.*]] = call i3 @llvm.ctlz.i3(i3 [[VAL:%.*]], i1 false)<br>
; CHECK-NEXT: [[VAL_NUMACTIVEBITS:%.*]] = sub nuw nsw i3 3, [[VAL_NUMLEADINGZEROS]]<br>
-; CHECK-NEXT: [[VAL_NUMACTIVEBITS_OFFSET:%.*]] = add nuw nsw i3 [[VAL_NUMACTIVEBITS]], 0<br>
-; CHECK-NEXT: [[IV_FINAL:%.*]] = call i3 @llvm.smax.i3(i3 [[VAL_NUMACTIVEBITS_OFFSET]], i3 [[START:%.*]])<br>
+; CHECK-NEXT: [[IV_FINAL:%.*]] = call i3 @llvm.smax.i3(i3 [[VAL_NUMACTIVEBITS]], i3 [[START:%.*]])<br>
; CHECK-NEXT: [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub nuw nsw i3 [[IV_FINAL]], [[START]]<br>
; CHECK-NEXT: [[LOOP_TRIPCOUNT:%.*]] = add nuw nsw i3 [[LOOP_BACKEDGETAKENCOUNT]], 1<br>
; CHECK-NEXT: br label [[LOOP:%.*]]<br>
<br>
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/induction-trunc.ll b/llvm/test/Transforms/LoopVectorize/AArch64/induction-trunc.ll<br>
index 2bee64107d7c9..b5094c112ce05 100644<br>
--- a/llvm/test/Transforms/LoopVectorize/AArch64/induction-trunc.ll<br>
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/induction-trunc.ll<br>
@@ -7,9 +7,8 @@ target triple = "aarch64--linux-gnu"<br>
; CHECK: vector.body:<br>
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %<a href="http://vector.ph" rel="noreferrer" target="_blank">vector.ph</a> ], [ [[INDEX_NEXT:%.*]], %vector.body ]<br>
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 5<br>
-; CHECK-NEXT: [[INDUCTION:%.*]] = add i64 [[OFFSET_IDX]], 0<br>
; CHECK-NEXT: [[INDUCTION1:%.*]] = add i64 [[OFFSET_IDX]], 5<br>
-; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[INDUCTION]] to i32<br>
+; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[OFFSET_IDX]] to i32<br>
; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[INDUCTION1]] to i32<br>
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2<br>
; CHECK: br i1 {{.*}}, label %middle.block, label %vector.body<br>
<br>
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/scalarize-store-with-predication.ll b/llvm/test/Transforms/LoopVectorize/AArch64/scalarize-store-with-predication.ll<br>
index cf0dbb30d0d37..2b97659a8a92b 100644<br>
--- a/llvm/test/Transforms/LoopVectorize/AArch64/scalarize-store-with-predication.ll<br>
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/scalarize-store-with-predication.ll<br>
@@ -22,11 +22,11 @@ define void @foo(i32* %data1, i32* %data2) {<br>
; CHECK-NEXT: store i32 {{%.*}}, i32* {{%.*}}<br>
; CHECK-NEXT: br label %pred.store.continue<br>
; CHECK: pred.store.continue:<br>
-; CHECK-NEXT: br i1 {{%.*}}, label %pred.store.if2, label %pred.store.continue3<br>
-; CHECK: pred.store.if2:<br>
+; CHECK-NEXT: br i1 {{%.*}}, label %pred.store.if1, label %pred.store.continue2<br>
+; CHECK: pred.store.if1:<br>
; CHECK-NEXT: store i32 {{%.*}}, i32* {{%.*}}<br>
-; CHECK-NEXT: br label %pred.store.continue3<br>
-; CHECK: pred.store.continue3:<br>
+; CHECK-NEXT: br label %pred.store.continue2<br>
+; CHECK: pred.store.continue2:<br>
<br>
entry:<br>
br label %while.body<br>
<br>
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll<br>
index 76a596d896149..7c2f64e10b5d0 100644<br>
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll<br>
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll<br>
@@ -42,16 +42,14 @@ define void @pointer_induction_used_as_vector(i8** noalias %start.1, i8* noalias<br>
; CHECK: vector.body:<br>
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]<br>
; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 0<br>
-; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 0<br>
-; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8*, i8** [[START_1]], i64 [[TMP5]]<br>
+; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8*, i8** [[START_1]], i64 [[INDEX]]<br>
; CHECK-NEXT: [[TMP6:%.*]] = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()<br>
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[INDEX]], i32 0<br>
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer<br>
; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 2 x i64> [[TMP6]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 0, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)<br>
; CHECK-NEXT: [[TMP8:%.*]] = add <vscale x 2 x i64> [[DOTSPLAT]], [[TMP7]]<br>
; CHECK-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, i8* [[START_2]], <vscale x 2 x i64> [[TMP8]]<br>
-; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 0<br>
-; CHECK-NEXT: [[NEXT_GEP5:%.*]] = getelementptr i8, i8* [[START_2]], i64 [[TMP9]]<br>
+; CHECK-NEXT: [[NEXT_GEP5:%.*]] = getelementptr i8, i8* [[START_2]], i64 [[INDEX]]<br>
; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 1<br>
; CHECK-NEXT: [[NEXT_GEP6:%.*]] = getelementptr i8, i8* [[START_2]], i64 [[TMP10]]<br>
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, <vscale x 2 x i8*> [[NEXT_GEP4]], i64 1<br>
@@ -129,8 +127,7 @@ define void @pointer_induction(i8* noalias %start, i64 %N) {<br>
; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 2 x i64> [[TMP5]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 0, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)<br>
; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 2 x i64> [[DOTSPLAT]], [[TMP6]]<br>
; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, i8* [[START]], <vscale x 2 x i64> [[TMP7]]<br>
-; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX1]], 0<br>
-; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, i8* [[START]], i64 [[TMP8]]<br>
+; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, i8* [[START]], i64 [[INDEX1]]<br>
; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX1]], 1<br>
; CHECK-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, i8* [[START]], i64 [[TMP9]]<br>
; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX1]], 0<br>
<br>
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-scalar-epilogue-fallback.ll b/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-scalar-epilogue-fallback.ll<br>
index 08325ea1047e9..1e271b4c79bfc 100644<br>
--- a/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-scalar-epilogue-fallback.ll<br>
+++ b/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-scalar-epilogue-fallback.ll<br>
@@ -25,18 +25,17 @@ define void @outside_user_blocks_tail_folding(i8* nocapture readonly %ptr, i32 %<br>
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]<br>
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i32 [[SIZE]], [[INDEX]]<br>
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[OFFSET_IDX]], 0<br>
-; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 0<br>
-; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, i8* [[PTR]], i32 [[TMP1]]<br>
-; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8* [[NEXT_GEP]], i32 1<br>
-; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i32 0<br>
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8* [[TMP3]] to <16 x i8>*<br>
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, <16 x i8>* [[TMP4]], align 1<br>
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, i8* [[NEXT_GEP]], i32 0<br>
-; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to <16 x i8>*<br>
-; CHECK-NEXT: store <16 x i8> [[WIDE_LOAD]], <16 x i8>* [[TMP6]], align 1<br>
+; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, i8* [[PTR]], i32 [[INDEX]]<br>
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, i8* [[NEXT_GEP]], i32 1<br>
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8* [[TMP1]], i32 0<br>
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to <16 x i8>*<br>
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, <16 x i8>* [[TMP3]], align 1<br>
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[NEXT_GEP]], i32 0<br>
+; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to <16 x i8>*<br>
+; CHECK-NEXT: store <16 x i8> [[WIDE_LOAD]], <16 x i8>* [[TMP5]], align 1<br>
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16<br>
-; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]<br>
-; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !0<br>
+; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]<br>
+; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]<br>
; CHECK: middle.block:<br>
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[SIZE]], [[N_VEC]]<br>
; CHECK-NEXT: br i1 [[CMP_N]], label [[END:%.*]], label [[SCALAR_PH]]<br>
@@ -49,10 +48,10 @@ define void @outside_user_blocks_tail_folding(i8* nocapture readonly %ptr, i32 %<br>
; CHECK-NEXT: [[BUFF:%.*]] = phi i8* [ [[INCDEC_PTR:%.*]], [[BODY]] ], [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ]<br>
; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i8, i8* [[BUFF]], i32 1<br>
; CHECK-NEXT: [[DEC]] = add nsw i32 [[DEC66]], -1<br>
-; CHECK-NEXT: [[TMP8:%.*]] = load i8, i8* [[INCDEC_PTR]], align 1<br>
-; CHECK-NEXT: store i8 [[TMP8]], i8* [[BUFF]], align 1<br>
+; CHECK-NEXT: [[TMP7:%.*]] = load i8, i8* [[INCDEC_PTR]], align 1<br>
+; CHECK-NEXT: store i8 [[TMP7]], i8* [[BUFF]], align 1<br>
; CHECK-NEXT: [[TOBOOL11:%.*]] = icmp eq i32 [[DEC]], 0<br>
-; CHECK-NEXT: br i1 [[TOBOOL11]], label [[END]], label [[BODY]], !llvm.loop !2<br>
+; CHECK-NEXT: br i1 [[TOBOOL11]], label [[END]], label [[BODY]], !llvm.loop [[LOOP2:![0-9]+]]<br>
; CHECK: end:<br>
; CHECK-NEXT: [[INCDEC_PTR_LCSSA:%.*]] = phi i8* [ [[INCDEC_PTR]], [[BODY]] ], [ [[IND_END2]], [[MIDDLE_BLOCK]] ]<br>
; CHECK-NEXT: store i8* [[INCDEC_PTR_LCSSA]], i8** [[POS]], align 4<br>
<br>
diff --git a/llvm/test/Transforms/LoopVectorize/X86/cost-model-assert.ll b/llvm/test/Transforms/LoopVectorize/X86/cost-model-assert.ll<br>
index 20980c520a3cc..223b6e134f747 100644<br>
--- a/llvm/test/Transforms/LoopVectorize/X86/cost-model-assert.ll<br>
+++ b/llvm/test/Transforms/LoopVectorize/X86/cost-model-assert.ll<br>
@@ -34,53 +34,52 @@ define void @cff_index_load_offsets(i1 %cond, i8 %x, i8* %p) #0 {<br>
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]<br>
; CHECK: vector.body:<br>
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]<br>
-; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 0<br>
-; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 4<br>
-; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, i8* null, i64 [[TMP5]]<br>
-; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 4<br>
-; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[TMP6]], 4<br>
-; CHECK-NEXT: [[NEXT_GEP1:%.*]] = getelementptr i8, i8* null, i64 [[TMP7]]<br>
-; CHECK-NEXT: [[TMP8:%.*]] = zext <4 x i8> [[BROADCAST_SPLAT]] to <4 x i32><br>
-; CHECK-NEXT: [[TMP9:%.*]] = zext <4 x i8> [[BROADCAST_SPLAT3]] to <4 x i32><br>
+; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[INDEX]], 4<br>
+; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, i8* null, i64 [[TMP4]]<br>
+; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 4<br>
+; CHECK-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], 4<br>
+; CHECK-NEXT: [[NEXT_GEP1:%.*]] = getelementptr i8, i8* null, i64 [[TMP6]]<br>
+; CHECK-NEXT: [[TMP7:%.*]] = zext <4 x i8> [[BROADCAST_SPLAT]] to <4 x i32><br>
+; CHECK-NEXT: [[TMP8:%.*]] = zext <4 x i8> [[BROADCAST_SPLAT3]] to <4 x i32><br>
+; CHECK-NEXT: [[TMP9:%.*]] = shl nuw <4 x i32> [[TMP7]], <i32 24, i32 24, i32 24, i32 24><br>
; CHECK-NEXT: [[TMP10:%.*]] = shl nuw <4 x i32> [[TMP8]], <i32 24, i32 24, i32 24, i32 24><br>
-; CHECK-NEXT: [[TMP11:%.*]] = shl nuw <4 x i32> [[TMP9]], <i32 24, i32 24, i32 24, i32 24><br>
-; CHECK-NEXT: [[TMP12:%.*]] = load i8, i8* [[P:%.*]], align 1, !tbaa [[TBAA1:![0-9]+]]<br>
-; CHECK-NEXT: [[BROADCAST_SPLATINSERT4:%.*]] = insertelement <4 x i8> poison, i8 [[TMP12]], i32 0<br>
+; CHECK-NEXT: [[TMP11:%.*]] = load i8, i8* [[P:%.*]], align 1, !tbaa [[TBAA1:![0-9]+]]<br>
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT4:%.*]] = insertelement <4 x i8> poison, i8 [[TMP11]], i32 0<br>
; CHECK-NEXT: [[BROADCAST_SPLAT5:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLATINSERT4]], <4 x i8> poison, <4 x i32> zeroinitializer<br>
-; CHECK-NEXT: [[TMP13:%.*]] = load i8, i8* [[P]], align 1, !tbaa [[TBAA1]]<br>
-; CHECK-NEXT: [[BROADCAST_SPLATINSERT6:%.*]] = insertelement <4 x i8> poison, i8 [[TMP13]], i32 0<br>
+; CHECK-NEXT: [[TMP12:%.*]] = load i8, i8* [[P]], align 1, !tbaa [[TBAA1]]<br>
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT6:%.*]] = insertelement <4 x i8> poison, i8 [[TMP12]], i32 0<br>
; CHECK-NEXT: [[BROADCAST_SPLAT7:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLATINSERT6]], <4 x i8> poison, <4 x i32> zeroinitializer<br>
-; CHECK-NEXT: [[TMP14:%.*]] = zext <4 x i8> [[BROADCAST_SPLAT5]] to <4 x i32><br>
-; CHECK-NEXT: [[TMP15:%.*]] = zext <4 x i8> [[BROADCAST_SPLAT7]] to <4 x i32><br>
+; CHECK-NEXT: [[TMP13:%.*]] = zext <4 x i8> [[BROADCAST_SPLAT5]] to <4 x i32><br>
+; CHECK-NEXT: [[TMP14:%.*]] = zext <4 x i8> [[BROADCAST_SPLAT7]] to <4 x i32><br>
+; CHECK-NEXT: [[TMP15:%.*]] = shl nuw nsw <4 x i32> [[TMP13]], <i32 16, i32 16, i32 16, i32 16><br>
; CHECK-NEXT: [[TMP16:%.*]] = shl nuw nsw <4 x i32> [[TMP14]], <i32 16, i32 16, i32 16, i32 16><br>
-; CHECK-NEXT: [[TMP17:%.*]] = shl nuw nsw <4 x i32> [[TMP15]], <i32 16, i32 16, i32 16, i32 16><br>
+; CHECK-NEXT: [[TMP17:%.*]] = or <4 x i32> [[TMP15]], [[TMP9]]<br>
; CHECK-NEXT: [[TMP18:%.*]] = or <4 x i32> [[TMP16]], [[TMP10]]<br>
-; CHECK-NEXT: [[TMP19:%.*]] = or <4 x i32> [[TMP17]], [[TMP11]]<br>
+; CHECK-NEXT: [[TMP19:%.*]] = load i8, i8* undef, align 1, !tbaa [[TBAA1]]<br>
; CHECK-NEXT: [[TMP20:%.*]] = load i8, i8* undef, align 1, !tbaa [[TBAA1]]<br>
-; CHECK-NEXT: [[TMP21:%.*]] = load i8, i8* undef, align 1, !tbaa [[TBAA1]]<br>
+; CHECK-NEXT: [[TMP21:%.*]] = or <4 x i32> [[TMP17]], zeroinitializer<br>
; CHECK-NEXT: [[TMP22:%.*]] = or <4 x i32> [[TMP18]], zeroinitializer<br>
-; CHECK-NEXT: [[TMP23:%.*]] = or <4 x i32> [[TMP19]], zeroinitializer<br>
+; CHECK-NEXT: [[TMP23:%.*]] = or <4 x i32> [[TMP21]], zeroinitializer<br>
; CHECK-NEXT: [[TMP24:%.*]] = or <4 x i32> [[TMP22]], zeroinitializer<br>
-; CHECK-NEXT: [[TMP25:%.*]] = or <4 x i32> [[TMP23]], zeroinitializer<br>
-; CHECK-NEXT: [[TMP26:%.*]] = extractelement <4 x i32> [[TMP24]], i32 0<br>
-; CHECK-NEXT: store i32 [[TMP26]], i32* undef, align 4, !tbaa [[TBAA4:![0-9]+]]<br>
-; CHECK-NEXT: [[TMP27:%.*]] = extractelement <4 x i32> [[TMP24]], i32 1<br>
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <4 x i32> [[TMP23]], i32 0<br>
+; CHECK-NEXT: store i32 [[TMP25]], i32* undef, align 4, !tbaa [[TBAA4:![0-9]+]]<br>
+; CHECK-NEXT: [[TMP26:%.*]] = extractelement <4 x i32> [[TMP23]], i32 1<br>
+; CHECK-NEXT: store i32 [[TMP26]], i32* undef, align 4, !tbaa [[TBAA4]]<br>
+; CHECK-NEXT: [[TMP27:%.*]] = extractelement <4 x i32> [[TMP23]], i32 2<br>
; CHECK-NEXT: store i32 [[TMP27]], i32* undef, align 4, !tbaa [[TBAA4]]<br>
-; CHECK-NEXT: [[TMP28:%.*]] = extractelement <4 x i32> [[TMP24]], i32 2<br>
+; CHECK-NEXT: [[TMP28:%.*]] = extractelement <4 x i32> [[TMP23]], i32 3<br>
; CHECK-NEXT: store i32 [[TMP28]], i32* undef, align 4, !tbaa [[TBAA4]]<br>
-; CHECK-NEXT: [[TMP29:%.*]] = extractelement <4 x i32> [[TMP24]], i32 3<br>
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <4 x i32> [[TMP24]], i32 0<br>
; CHECK-NEXT: store i32 [[TMP29]], i32* undef, align 4, !tbaa [[TBAA4]]<br>
-; CHECK-NEXT: [[TMP30:%.*]] = extractelement <4 x i32> [[TMP25]], i32 0<br>
+; CHECK-NEXT: [[TMP30:%.*]] = extractelement <4 x i32> [[TMP24]], i32 1<br>
; CHECK-NEXT: store i32 [[TMP30]], i32* undef, align 4, !tbaa [[TBAA4]]<br>
-; CHECK-NEXT: [[TMP31:%.*]] = extractelement <4 x i32> [[TMP25]], i32 1<br>
+; CHECK-NEXT: [[TMP31:%.*]] = extractelement <4 x i32> [[TMP24]], i32 2<br>
; CHECK-NEXT: store i32 [[TMP31]], i32* undef, align 4, !tbaa [[TBAA4]]<br>
-; CHECK-NEXT: [[TMP32:%.*]] = extractelement <4 x i32> [[TMP25]], i32 2<br>
+; CHECK-NEXT: [[TMP32:%.*]] = extractelement <4 x i32> [[TMP24]], i32 3<br>
; CHECK-NEXT: store i32 [[TMP32]], i32* undef, align 4, !tbaa [[TBAA4]]<br>
-; CHECK-NEXT: [[TMP33:%.*]] = extractelement <4 x i32> [[TMP25]], i32 3<br>
-; CHECK-NEXT: store i32 [[TMP33]], i32* undef, align 4, !tbaa [[TBAA4]]<br>
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8<br>
-; CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]<br>
-; CHECK-NEXT: br i1 [[TMP34]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]<br>
+; CHECK-NEXT: [[TMP33:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]<br>
+; CHECK-NEXT: br i1 [[TMP33]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]<br>
; CHECK: middle.block:<br>
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]]<br>
; CHECK-NEXT: br i1 [[CMP_N]], label [[SW_EPILOG:%.*]], label [[SCALAR_PH]]<br>
@@ -91,11 +90,11 @@ define void @cff_index_load_offsets(i1 %cond, i8 %x, i8* %p) #0 {<br>
; CHECK-NEXT: [[P_359:%.*]] = phi i8* [ [[ADD_PTR86:%.*]], [[FOR_BODY68]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]<br>
; CHECK-NEXT: [[CONV70:%.*]] = zext i8 [[X]] to i32<br>
; CHECK-NEXT: [[SHL71:%.*]] = shl nuw i32 [[CONV70]], 24<br>
-; CHECK-NEXT: [[TMP35:%.*]] = load i8, i8* [[P]], align 1, !tbaa [[TBAA1]]<br>
-; CHECK-NEXT: [[CONV73:%.*]] = zext i8 [[TMP35]] to i32<br>
+; CHECK-NEXT: [[TMP34:%.*]] = load i8, i8* [[P]], align 1, !tbaa [[TBAA1]]<br>
+; CHECK-NEXT: [[CONV73:%.*]] = zext i8 [[TMP34]] to i32<br>
; CHECK-NEXT: [[SHL74:%.*]] = shl nuw nsw i32 [[CONV73]], 16<br>
; CHECK-NEXT: [[OR75:%.*]] = or i32 [[SHL74]], [[SHL71]]<br>
-; CHECK-NEXT: [[TMP36:%.*]] = load i8, i8* undef, align 1, !tbaa [[TBAA1]]<br>
+; CHECK-NEXT: [[TMP35:%.*]] = load i8, i8* undef, align 1, !tbaa [[TBAA1]]<br>
; CHECK-NEXT: [[SHL78:%.*]] = shl nuw nsw i32 undef, 8<br>
; CHECK-NEXT: [[OR79:%.*]] = or i32 [[OR75]], [[SHL78]]<br>
; CHECK-NEXT: [[CONV81:%.*]] = zext i8 undef to i32<br>
<br>
diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll<br>
index c4a17acdb0428..a12680ab49884 100644<br>
--- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll<br>
+++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll<br>
@@ -645,37 +645,36 @@ define void @sink_dominance(i32* %ptr, i32 %N) {<br>
; CHECK: vector.scevcheck:<br>
; CHECK-NEXT: [[UMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[N]], i32 1)<br>
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[UMAX]], -1<br>
-; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 0<br>
-; CHECK-NEXT: [[TMP2:%.*]] = sub i32 0, [[TMP0]]<br>
-; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[TMP2]], 0<br>
-; CHECK-NEXT: [[TMP4:%.*]] = icmp slt i32 [[TMP1]], 0<br>
-; CHECK-NEXT: br i1 [[TMP4]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]<br>
+; CHECK-NEXT: [[TMP1:%.*]] = sub i32 0, [[TMP0]]<br>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], 0<br>
+; CHECK-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP0]], 0<br>
+; CHECK-NEXT: br i1 [[TMP3]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]<br>
; CHECK: <a href="http://vector.ph" rel="noreferrer" target="_blank">vector.ph</a>:<br>
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[UMAX1]], 4<br>
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[UMAX1]], [[N_MOD_VF]]<br>
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]<br>
; CHECK: vector.body:<br>
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]<br>
-; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <4 x i64> [ <i64 poison, i64 poison, i64 poison, i64 0>, [[VECTOR_PH]] ], [ [[TMP9:%.*]], [[VECTOR_BODY]] ]<br>
-; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[INDEX]], 0<br>
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[PTR:%.*]], i32 [[TMP5]]<br>
-; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, i32* [[TMP6]], i32 0<br>
-; CHECK-NEXT: [[TMP8:%.*]] = bitcast i32* [[TMP7]] to <4 x i32>*<br>
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP8]], align 4<br>
-; CHECK-NEXT: [[TMP9]] = zext <4 x i32> [[WIDE_LOAD]] to <4 x i64><br>
-; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x i64> [[VECTOR_RECUR]], <4 x i64> [[TMP9]], <4 x i32> <i32 3, i32 4, i32 5, i32 6><br>
-; CHECK-NEXT: [[TMP11:%.*]] = trunc <4 x i64> [[TMP10]] to <4 x i32><br>
-; CHECK-NEXT: [[TMP12:%.*]] = icmp slt <4 x i32> [[TMP11]], <i32 213, i32 213, i32 213, i32 213><br>
-; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[TMP12]], <4 x i32> [[TMP11]], <4 x i32> <i32 22, i32 22, i32 22, i32 22><br>
-; CHECK-NEXT: [[TMP14:%.*]] = bitcast i32* [[TMP7]] to <4 x i32>*<br>
-; CHECK-NEXT: store <4 x i32> [[TMP13]], <4 x i32>* [[TMP14]], align 4<br>
+; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <4 x i64> [ <i64 poison, i64 poison, i64 poison, i64 0>, [[VECTOR_PH]] ], [ [[TMP8:%.*]], [[VECTOR_BODY]] ]<br>
+; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[INDEX]], 0<br>
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[PTR:%.*]], i32 [[TMP4]]<br>
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[TMP5]], i32 0<br>
+; CHECK-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP6]] to <4 x i32>*<br>
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP7]], align 4<br>
+; CHECK-NEXT: [[TMP8]] = zext <4 x i32> [[WIDE_LOAD]] to <4 x i64><br>
+; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x i64> [[VECTOR_RECUR]], <4 x i64> [[TMP8]], <4 x i32> <i32 3, i32 4, i32 5, i32 6><br>
+; CHECK-NEXT: [[TMP10:%.*]] = trunc <4 x i64> [[TMP9]] to <4 x i32><br>
+; CHECK-NEXT: [[TMP11:%.*]] = icmp slt <4 x i32> [[TMP10]], <i32 213, i32 213, i32 213, i32 213><br>
+; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[TMP11]], <4 x i32> [[TMP10]], <4 x i32> <i32 22, i32 22, i32 22, i32 22><br>
+; CHECK-NEXT: [[TMP13:%.*]] = bitcast i32* [[TMP6]] to <4 x i32>*<br>
+; CHECK-NEXT: store <4 x i32> [[TMP12]], <4 x i32>* [[TMP13]], align 4<br>
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4<br>
-; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]<br>
-; CHECK-NEXT: br i1 [[TMP15]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]<br>
+; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]<br>
+; CHECK-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]<br>
; CHECK: middle.block:<br>
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[UMAX1]], [[N_VEC]]<br>
-; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i64> [[TMP9]], i32 3<br>
-; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i64> [[TMP9]], i32 2<br>
+; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i64> [[TMP8]], i32 3<br>
+; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i64> [[TMP8]], i32 2<br>
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]<br>
; CHECK: <a href="http://scalar.ph" rel="noreferrer" target="_blank">scalar.ph</a>:<br>
; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ENTRY:%.*]] ], [ [[VECTOR_RECUR_EXTRACT]], [[MIDDLE_BLOCK]] ]<br>
@@ -732,39 +731,38 @@ define void @sink_dominance_2(i32* %ptr, i32 %N) {<br>
; CHECK: vector.scevcheck:<br>
; CHECK-NEXT: [[UMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[N]], i32 1)<br>
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[UMAX]], -1<br>
-; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 0<br>
-; CHECK-NEXT: [[TMP2:%.*]] = sub i32 0, [[TMP0]]<br>
-; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[TMP2]], 0<br>
-; CHECK-NEXT: [[TMP4:%.*]] = icmp slt i32 [[TMP1]], 0<br>
-; CHECK-NEXT: br i1 [[TMP4]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]<br>
+; CHECK-NEXT: [[TMP1:%.*]] = sub i32 0, [[TMP0]]<br>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], 0<br>
+; CHECK-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP0]], 0<br>
+; CHECK-NEXT: br i1 [[TMP3]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]<br>
; CHECK: <a href="http://vector.ph" rel="noreferrer" target="_blank">vector.ph</a>:<br>
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[UMAX1]], 4<br>
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[UMAX1]], [[N_MOD_VF]]<br>
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]<br>
; CHECK: vector.body:<br>
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]<br>
-; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <4 x i64> [ <i64 poison, i64 poison, i64 poison, i64 0>, [[VECTOR_PH]] ], [ [[TMP9:%.*]], [[VECTOR_BODY]] ]<br>
-; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[INDEX]], 0<br>
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[PTR:%.*]], i32 [[TMP5]]<br>
-; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, i32* [[TMP6]], i32 0<br>
-; CHECK-NEXT: [[TMP8:%.*]] = bitcast i32* [[TMP7]] to <4 x i32>*<br>
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP8]], align 4<br>
-; CHECK-NEXT: [[TMP9]] = zext <4 x i32> [[WIDE_LOAD]] to <4 x i64><br>
-; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x i64> [[VECTOR_RECUR]], <4 x i64> [[TMP9]], <4 x i32> <i32 3, i32 4, i32 5, i32 6><br>
-; CHECK-NEXT: [[TMP11:%.*]] = trunc <4 x i64> [[TMP10]] to <4 x i32><br>
-; CHECK-NEXT: [[TMP12:%.*]] = add <4 x i32> [[TMP11]], <i32 2, i32 2, i32 2, i32 2><br>
-; CHECK-NEXT: [[TMP13:%.*]] = mul <4 x i32> [[TMP12]], <i32 99, i32 99, i32 99, i32 99><br>
-; CHECK-NEXT: [[TMP14:%.*]] = icmp slt <4 x i32> [[TMP11]], <i32 213, i32 213, i32 213, i32 213><br>
-; CHECK-NEXT: [[TMP15:%.*]] = select <4 x i1> [[TMP14]], <4 x i32> [[TMP11]], <4 x i32> [[TMP13]]<br>
-; CHECK-NEXT: [[TMP16:%.*]] = bitcast i32* [[TMP7]] to <4 x i32>*<br>
-; CHECK-NEXT: store <4 x i32> [[TMP15]], <4 x i32>* [[TMP16]], align 4<br>
+; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <4 x i64> [ <i64 poison, i64 poison, i64 poison, i64 0>, [[VECTOR_PH]] ], [ [[TMP8:%.*]], [[VECTOR_BODY]] ]<br>
+; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[INDEX]], 0<br>
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[PTR:%.*]], i32 [[TMP4]]<br>
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[TMP5]], i32 0<br>
+; CHECK-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP6]] to <4 x i32>*<br>
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP7]], align 4<br>
+; CHECK-NEXT: [[TMP8]] = zext <4 x i32> [[WIDE_LOAD]] to <4 x i64><br>
+; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x i64> [[VECTOR_RECUR]], <4 x i64> [[TMP8]], <4 x i32> <i32 3, i32 4, i32 5, i32 6><br>
+; CHECK-NEXT: [[TMP10:%.*]] = trunc <4 x i64> [[TMP9]] to <4 x i32><br>
+; CHECK-NEXT: [[TMP11:%.*]] = add <4 x i32> [[TMP10]], <i32 2, i32 2, i32 2, i32 2><br>
+; CHECK-NEXT: [[TMP12:%.*]] = mul <4 x i32> [[TMP11]], <i32 99, i32 99, i32 99, i32 99><br>
+; CHECK-NEXT: [[TMP13:%.*]] = icmp slt <4 x i32> [[TMP10]], <i32 213, i32 213, i32 213, i32 213><br>
+; CHECK-NEXT: [[TMP14:%.*]] = select <4 x i1> [[TMP13]], <4 x i32> [[TMP10]], <4 x i32> [[TMP12]]<br>
+; CHECK-NEXT: [[TMP15:%.*]] = bitcast i32* [[TMP6]] to <4 x i32>*<br>
+; CHECK-NEXT: store <4 x i32> [[TMP14]], <4 x i32>* [[TMP15]], align 4<br>
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4<br>
-; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]<br>
-; CHECK-NEXT: br i1 [[TMP17]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]<br>
+; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]<br>
+; CHECK-NEXT: br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]<br>
; CHECK: middle.block:<br>
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[UMAX1]], [[N_VEC]]<br>
-; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i64> [[TMP9]], i32 3<br>
-; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i64> [[TMP9]], i32 2<br>
+; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i64> [[TMP8]], i32 3<br>
+; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i64> [[TMP8]], i32 2<br>
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]<br>
; CHECK: <a href="http://scalar.ph" rel="noreferrer" target="_blank">scalar.ph</a>:<br>
; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ENTRY:%.*]] ], [ [[VECTOR_RECUR_EXTRACT]], [[MIDDLE_BLOCK]] ]<br>
<br>
diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll<br>
index c65f62cef65ef..7f2f18ea185c8 100644<br>
--- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll<br>
+++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll<br>
@@ -378,10 +378,9 @@ for.end:<br>
; Check the case when unrolled but not vectorized.<br>
; UNROLL-NO-VF-LABEL: extract_second_last_iteration<br>
; UNROLL-NO-VF: vector.body:<br>
-; UNROLL-NO-VF: %induction = add i32 %index, 0<br>
-; UNROLL-NO-VF: %induction1 = add i32 %index, 1<br>
-; UNROLL-NO-VF: %[[L1:.+]] = add i32 %induction, %x<br>
-; UNROLL-NO-VF: %[[L2:.+]] = add i32 %induction1, %x<br>
+; UNROLL-NO-VF: %induction = add i32 %index, 1<br>
+; UNROLL-NO-VF: %[[L1:.+]] = add i32 %index, %x<br>
+; UNROLL-NO-VF: %[[L2:.+]] = add i32 %induction, %x<br>
; UNROLL-NO-VF: %index.next = add nuw i32 %index, 2<br>
; UNROLL-NO-VF: icmp eq i32 %index.next, 96<br>
; UNROLL-NO-VF: for.end:<br>
<br>
diff --git a/llvm/test/Transforms/LoopVectorize/if-pred-stores.ll b/llvm/test/Transforms/LoopVectorize/if-pred-stores.ll<br>
index 0b84468dfa6e1..30bb3f7bb5116 100644<br>
--- a/llvm/test/Transforms/LoopVectorize/if-pred-stores.ll<br>
+++ b/llvm/test/Transforms/LoopVectorize/if-pred-stores.ll<br>
@@ -11,11 +11,10 @@ define i32 @test(i32* nocapture %f) #0 {<br>
; UNROLL-NEXT: entry:<br>
; UNROLL-NEXT: br label [[VECTOR_BODY:%.*]]<br>
; UNROLL: vector.body:<br>
-; UNROLL-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE3:%.*]] ]<br>
-; UNROLL-NEXT: [[INDUCTION:%.*]] = add i64 [[INDEX]], 0<br>
-; UNROLL-NEXT: [[INDUCTION1:%.*]] = add i64 [[INDEX]], 1<br>
-; UNROLL-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, i32* [[F:%.*]], i64 [[INDUCTION]]<br>
-; UNROLL-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[F]], i64 [[INDUCTION1]]<br>
+; UNROLL-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE2:%.*]] ]<br>
+; UNROLL-NEXT: [[INDUCTION:%.*]] = add i64 [[INDEX]], 1<br>
+; UNROLL-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, i32* [[F:%.*]], i64 [[INDEX]]<br>
+; UNROLL-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[F]], i64 [[INDUCTION]]<br>
; UNROLL-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP0]], align 4<br>
; UNROLL-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 4<br>
; UNROLL-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[TMP2]], 100<br>
@@ -26,12 +25,12 @@ define i32 @test(i32* nocapture %f) #0 {<br>
; UNROLL-NEXT: store i32 [[TMP6]], i32* [[TMP0]], align 4<br>
; UNROLL-NEXT: br label [[PRED_STORE_CONTINUE]]<br>
; UNROLL: pred.store.continue:<br>
-; UNROLL-NEXT: br i1 [[TMP5]], label [[PRED_STORE_IF2:%.*]], label [[PRED_STORE_CONTINUE3]]<br>
-; UNROLL: pred.store.if2:<br>
+; UNROLL-NEXT: br i1 [[TMP5]], label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2]]<br>
+; UNROLL: pred.store.if1:<br>
; UNROLL-NEXT: [[TMP7:%.*]] = add nsw i32 [[TMP3]], 20<br>
; UNROLL-NEXT: store i32 [[TMP7]], i32* [[TMP1]], align 4<br>
-; UNROLL-NEXT: br label [[PRED_STORE_CONTINUE3]]<br>
-; UNROLL: pred.store.continue3:<br>
+; UNROLL-NEXT: br label [[PRED_STORE_CONTINUE2]]<br>
+; UNROLL: pred.store.continue2:<br>
; UNROLL-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2<br>
; UNROLL-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128<br>
; UNROLL-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]<br>
@@ -61,11 +60,10 @@ define i32 @test(i32* nocapture %f) #0 {<br>
; UNROLL-NOSIMPLIFY: <a href="http://vector.ph" rel="noreferrer" target="_blank">vector.ph</a>:<br>
; UNROLL-NOSIMPLIFY-NEXT: br label [[VECTOR_BODY:%.*]]<br>
; UNROLL-NOSIMPLIFY: vector.body:<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE3:%.*]] ]<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION:%.*]] = add i64 [[INDEX]], 0<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION1:%.*]] = add i64 [[INDEX]], 1<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, i32* [[F:%.*]], i64 [[INDUCTION]]<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[F]], i64 [[INDUCTION1]]<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE2:%.*]] ]<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION:%.*]] = add i64 [[INDEX]], 1<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, i32* [[F:%.*]], i64 [[INDEX]]<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[F]], i64 [[INDUCTION]]<br>
; UNROLL-NOSIMPLIFY-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP0]], align 4<br>
; UNROLL-NOSIMPLIFY-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 4<br>
; UNROLL-NOSIMPLIFY-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[TMP2]], 100<br>
@@ -76,12 +74,12 @@ define i32 @test(i32* nocapture %f) #0 {<br>
; UNROLL-NOSIMPLIFY-NEXT: store i32 [[TMP6]], i32* [[TMP0]], align 4<br>
; UNROLL-NOSIMPLIFY-NEXT: br label [[PRED_STORE_CONTINUE]]<br>
; UNROLL-NOSIMPLIFY: pred.store.continue:<br>
-; UNROLL-NOSIMPLIFY-NEXT: br i1 [[TMP5]], label [[PRED_STORE_IF2:%.*]], label [[PRED_STORE_CONTINUE3]]<br>
-; UNROLL-NOSIMPLIFY: pred.store.if2:<br>
+; UNROLL-NOSIMPLIFY-NEXT: br i1 [[TMP5]], label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2]]<br>
+; UNROLL-NOSIMPLIFY: pred.store.if1:<br>
; UNROLL-NOSIMPLIFY-NEXT: [[TMP7:%.*]] = add nsw i32 [[TMP3]], 20<br>
; UNROLL-NOSIMPLIFY-NEXT: store i32 [[TMP7]], i32* [[TMP1]], align 4<br>
-; UNROLL-NOSIMPLIFY-NEXT: br label [[PRED_STORE_CONTINUE3]]<br>
-; UNROLL-NOSIMPLIFY: pred.store.continue3:<br>
+; UNROLL-NOSIMPLIFY-NEXT: br label [[PRED_STORE_CONTINUE2]]<br>
+; UNROLL-NOSIMPLIFY: pred.store.continue2:<br>
; UNROLL-NOSIMPLIFY-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2<br>
; UNROLL-NOSIMPLIFY-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128<br>
; UNROLL-NOSIMPLIFY-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]<br>
@@ -209,30 +207,29 @@ define void @bug18724(i1 %cond) {<br>
; UNROLL-NEXT: [[IND_END:%.*]] = add i64 [[N_VEC]], undef<br>
; UNROLL-NEXT: br label [[VECTOR_BODY:%.*]]<br>
; UNROLL: vector.body:<br>
-; UNROLL-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE4:%.*]] ]<br>
-; UNROLL-NEXT: [[VEC_PHI:%.*]] = phi i32 [ undef, [[VECTOR_PH]] ], [ [[PREDPHI:%.*]], [[PRED_STORE_CONTINUE4]] ]<br>
-; UNROLL-NEXT: [[VEC_PHI2:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[PREDPHI5:%.*]], [[PRED_STORE_CONTINUE4]] ]<br>
+; UNROLL-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE3:%.*]] ]<br>
+; UNROLL-NEXT: [[VEC_PHI:%.*]] = phi i32 [ undef, [[VECTOR_PH]] ], [ [[PREDPHI:%.*]], [[PRED_STORE_CONTINUE3]] ]<br>
+; UNROLL-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[PREDPHI4:%.*]], [[PRED_STORE_CONTINUE3]] ]<br>
; UNROLL-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[INDEX]], undef<br>
-; UNROLL-NEXT: [[INDUCTION:%.*]] = add i64 [[OFFSET_IDX]], 0<br>
-; UNROLL-NEXT: [[INDUCTION1:%.*]] = add i64 [[OFFSET_IDX]], 1<br>
-; UNROLL-NEXT: [[TMP4:%.*]] = getelementptr inbounds [768 x i32], [768 x i32]* undef, i64 0, i64 [[INDUCTION]]<br>
-; UNROLL-NEXT: [[TMP5:%.*]] = getelementptr inbounds [768 x i32], [768 x i32]* undef, i64 0, i64 [[INDUCTION1]]<br>
+; UNROLL-NEXT: [[INDUCTION:%.*]] = add i64 [[OFFSET_IDX]], 1<br>
+; UNROLL-NEXT: [[TMP4:%.*]] = getelementptr inbounds [768 x i32], [768 x i32]* undef, i64 0, i64 [[OFFSET_IDX]]<br>
+; UNROLL-NEXT: [[TMP5:%.*]] = getelementptr inbounds [768 x i32], [768 x i32]* undef, i64 0, i64 [[INDUCTION]]<br>
; UNROLL-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP4]], align 4<br>
; UNROLL-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP5]], align 4<br>
-; UNROLL-NEXT: br i1 undef, label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE4]]<br>
+; UNROLL-NEXT: br i1 undef, label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE3]]<br>
; UNROLL: pred.store.if:<br>
; UNROLL-NEXT: store i32 2, i32* [[TMP4]], align 4<br>
-; UNROLL-NEXT: br label [[PRED_STORE_CONTINUE4]]<br>
-; UNROLL: pred.store.continue4:<br>
+; UNROLL-NEXT: br label [[PRED_STORE_CONTINUE3]]<br>
+; UNROLL: pred.store.continue3:<br>
; UNROLL-NEXT: [[TMP8:%.*]] = add i32 [[VEC_PHI]], 1<br>
-; UNROLL-NEXT: [[TMP9:%.*]] = add i32 [[VEC_PHI2]], 1<br>
+; UNROLL-NEXT: [[TMP9:%.*]] = add i32 [[VEC_PHI1]], 1<br>
; UNROLL-NEXT: [[PREDPHI]] = select i1 undef, i32 [[VEC_PHI]], i32 [[TMP8]]<br>
-; UNROLL-NEXT: [[PREDPHI5]] = select i1 undef, i32 [[VEC_PHI2]], i32 [[TMP9]]<br>
+; UNROLL-NEXT: [[PREDPHI4]] = select i1 undef, i32 [[VEC_PHI1]], i32 [[TMP9]]<br>
; UNROLL-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2<br>
; UNROLL-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]<br>
; UNROLL-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]<br>
; UNROLL: middle.block:<br>
-; UNROLL-NEXT: [[BIN_RDX:%.*]] = add i32 [[PREDPHI5]], [[PREDPHI]]<br>
+; UNROLL-NEXT: [[BIN_RDX:%.*]] = add i32 [[PREDPHI4]], [[PREDPHI]]<br>
; UNROLL-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]<br>
; UNROLL-NEXT: [[TMP11:%.*]] = xor i1 [[CMP_N]], true<br>
; UNROLL-NEXT: call void @llvm.assume(i1 [[TMP11]])<br>
@@ -277,14 +274,13 @@ define void @bug18724(i1 %cond) {<br>
; UNROLL-NOSIMPLIFY-NEXT: [[IND_END:%.*]] = add i64 [[N_VEC]], undef<br>
; UNROLL-NOSIMPLIFY-NEXT: br label [[VECTOR_BODY:%.*]]<br>
; UNROLL-NOSIMPLIFY: vector.body:<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE4:%.*]] ]<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[VEC_PHI:%.*]] = phi i32 [ undef, [[VECTOR_PH]] ], [ [[PREDPHI:%.*]], [[PRED_STORE_CONTINUE4]] ]<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[VEC_PHI2:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[PREDPHI5:%.*]], [[PRED_STORE_CONTINUE4]] ]<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE3:%.*]] ]<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[VEC_PHI:%.*]] = phi i32 [ undef, [[VECTOR_PH]] ], [ [[PREDPHI:%.*]], [[PRED_STORE_CONTINUE3]] ]<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[PREDPHI4:%.*]], [[PRED_STORE_CONTINUE3]] ]<br>
; UNROLL-NOSIMPLIFY-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[INDEX]], undef<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION:%.*]] = add i64 [[OFFSET_IDX]], 0<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION1:%.*]] = add i64 [[OFFSET_IDX]], 1<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[TMP3:%.*]] = getelementptr inbounds [768 x i32], [768 x i32]* undef, i64 0, i64 [[INDUCTION]]<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[TMP4:%.*]] = getelementptr inbounds [768 x i32], [768 x i32]* undef, i64 0, i64 [[INDUCTION1]]<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION:%.*]] = add i64 [[OFFSET_IDX]], 1<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[TMP3:%.*]] = getelementptr inbounds [768 x i32], [768 x i32]* undef, i64 0, i64 [[OFFSET_IDX]]<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[TMP4:%.*]] = getelementptr inbounds [768 x i32], [768 x i32]* undef, i64 0, i64 [[INDUCTION]]<br>
; UNROLL-NOSIMPLIFY-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP3]], align 4<br>
; UNROLL-NOSIMPLIFY-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP4]], align 4<br>
; UNROLL-NOSIMPLIFY-NEXT: br i1 undef, label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]<br>
@@ -292,20 +288,20 @@ define void @bug18724(i1 %cond) {<br>
; UNROLL-NOSIMPLIFY-NEXT: store i32 2, i32* [[TMP3]], align 4<br>
; UNROLL-NOSIMPLIFY-NEXT: br label [[PRED_STORE_CONTINUE]]<br>
; UNROLL-NOSIMPLIFY: pred.store.continue:<br>
-; UNROLL-NOSIMPLIFY-NEXT: br i1 undef, label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4]]<br>
-; UNROLL-NOSIMPLIFY: pred.store.if3:<br>
+; UNROLL-NOSIMPLIFY-NEXT: br i1 undef, label [[PRED_STORE_IF2:%.*]], label [[PRED_STORE_CONTINUE3]]<br>
+; UNROLL-NOSIMPLIFY: pred.store.if2:<br>
; UNROLL-NOSIMPLIFY-NEXT: store i32 2, i32* [[TMP4]], align 4<br>
-; UNROLL-NOSIMPLIFY-NEXT: br label [[PRED_STORE_CONTINUE4]]<br>
-; UNROLL-NOSIMPLIFY: pred.store.continue4:<br>
+; UNROLL-NOSIMPLIFY-NEXT: br label [[PRED_STORE_CONTINUE3]]<br>
+; UNROLL-NOSIMPLIFY: pred.store.continue3:<br>
; UNROLL-NOSIMPLIFY-NEXT: [[TMP7:%.*]] = add i32 [[VEC_PHI]], 1<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[TMP8:%.*]] = add i32 [[VEC_PHI2]], 1<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[TMP8:%.*]] = add i32 [[VEC_PHI1]], 1<br>
; UNROLL-NOSIMPLIFY-NEXT: [[PREDPHI]] = select i1 undef, i32 [[VEC_PHI]], i32 [[TMP7]]<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[PREDPHI5]] = select i1 undef, i32 [[VEC_PHI2]], i32 [[TMP8]]<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[PREDPHI4]] = select i1 undef, i32 [[VEC_PHI1]], i32 [[TMP8]]<br>
; UNROLL-NOSIMPLIFY-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2<br>
; UNROLL-NOSIMPLIFY-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]<br>
; UNROLL-NOSIMPLIFY-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]<br>
; UNROLL-NOSIMPLIFY: middle.block:<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[BIN_RDX:%.*]] = add i32 [[PREDPHI5]], [[PREDPHI]]<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[BIN_RDX:%.*]] = add i32 [[PREDPHI4]], [[PREDPHI]]<br>
; UNROLL-NOSIMPLIFY-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]]<br>
; UNROLL-NOSIMPLIFY-NEXT: br i1 [[CMP_N]], label [[FOR_INC26_LOOPEXIT:%.*]], label [[SCALAR_PH]]<br>
; UNROLL-NOSIMPLIFY: <a href="http://scalar.ph" rel="noreferrer" target="_blank">scalar.ph</a>:<br>
@@ -437,26 +433,24 @@ define void @minimal_bit_widths(i1 %c) {<br>
; UNROLL-NEXT: entry:<br>
; UNROLL-NEXT: br label [[VECTOR_BODY:%.*]]<br>
; UNROLL: vector.body:<br>
-; UNROLL-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE6:%.*]] ]<br>
+; UNROLL-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE4:%.*]] ]<br>
; UNROLL-NEXT: [[OFFSET_IDX:%.*]] = sub i64 undef, [[INDEX]]<br>
-; UNROLL-NEXT: [[INDUCTION3:%.*]] = add i64 [[OFFSET_IDX]], 0<br>
-; UNROLL-NEXT: [[INDUCTION4:%.*]] = add i64 [[OFFSET_IDX]], -1<br>
-; UNROLL-NEXT: br i1 [[C:%.*]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE6]]<br>
+; UNROLL-NEXT: [[INDUCTION2:%.*]] = add i64 [[OFFSET_IDX]], -1<br>
+; UNROLL-NEXT: br i1 [[C:%.*]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE4]]<br>
; UNROLL: pred.store.if:<br>
-; UNROLL-NEXT: [[INDUCTION:%.*]] = add i64 [[INDEX]], 0<br>
-; UNROLL-NEXT: [[TMP0:%.*]] = getelementptr i8, i8* undef, i64 [[INDUCTION]]<br>
+; UNROLL-NEXT: [[TMP0:%.*]] = getelementptr i8, i8* undef, i64 [[INDEX]]<br>
; UNROLL-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1<br>
; UNROLL-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32<br>
; UNROLL-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8<br>
; UNROLL-NEXT: store i8 [[TMP3]], i8* [[TMP0]], align 1<br>
-; UNROLL-NEXT: [[INDUCTION2:%.*]] = add i64 [[INDEX]], 1<br>
-; UNROLL-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* undef, i64 [[INDUCTION2]]<br>
+; UNROLL-NEXT: [[INDUCTION:%.*]] = add i64 [[INDEX]], 1<br>
+; UNROLL-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* undef, i64 [[INDUCTION]]<br>
; UNROLL-NEXT: [[TMP5:%.*]] = load i8, i8* [[TMP4]], align 1<br>
; UNROLL-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i32<br>
; UNROLL-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i8<br>
; UNROLL-NEXT: store i8 [[TMP7]], i8* [[TMP4]], align 1<br>
-; UNROLL-NEXT: br label [[PRED_STORE_CONTINUE6]]<br>
-; UNROLL: pred.store.continue6:<br>
+; UNROLL-NEXT: br label [[PRED_STORE_CONTINUE4]]<br>
+; UNROLL: pred.store.continue4:<br>
; UNROLL-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2<br>
; UNROLL-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], undef<br>
; UNROLL-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]<br>
@@ -488,30 +482,28 @@ define void @minimal_bit_widths(i1 %c) {<br>
; UNROLL-NOSIMPLIFY: <a href="http://vector.ph" rel="noreferrer" target="_blank">vector.ph</a>:<br>
; UNROLL-NOSIMPLIFY-NEXT: br label [[VECTOR_BODY:%.*]]<br>
; UNROLL-NOSIMPLIFY: vector.body:<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE6:%.*]] ]<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE4:%.*]] ]<br>
; UNROLL-NOSIMPLIFY-NEXT: [[OFFSET_IDX:%.*]] = sub i64 undef, [[INDEX]]<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION3:%.*]] = add i64 [[OFFSET_IDX]], 0<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION4:%.*]] = add i64 [[OFFSET_IDX]], -1<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION2:%.*]] = add i64 [[OFFSET_IDX]], -1<br>
; UNROLL-NOSIMPLIFY-NEXT: br i1 [[C:%.*]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]<br>
; UNROLL-NOSIMPLIFY: pred.store.if:<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION:%.*]] = add i64 [[INDEX]], 0<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[TMP0:%.*]] = getelementptr i8, i8* undef, i64 [[INDUCTION]]<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[TMP0:%.*]] = getelementptr i8, i8* undef, i64 [[INDEX]]<br>
; UNROLL-NOSIMPLIFY-NEXT: [[TMP1:%.*]] = load i8, i8* [[TMP0]], align 1<br>
; UNROLL-NOSIMPLIFY-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32<br>
; UNROLL-NOSIMPLIFY-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8<br>
; UNROLL-NOSIMPLIFY-NEXT: store i8 [[TMP3]], i8* [[TMP0]], align 1<br>
; UNROLL-NOSIMPLIFY-NEXT: br label [[PRED_STORE_CONTINUE]]<br>
; UNROLL-NOSIMPLIFY: pred.store.continue:<br>
-; UNROLL-NOSIMPLIFY-NEXT: br i1 [[C]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6]]<br>
-; UNROLL-NOSIMPLIFY: pred.store.if5:<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION2:%.*]] = add i64 [[INDEX]], 1<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* undef, i64 [[INDUCTION2]]<br>
+; UNROLL-NOSIMPLIFY-NEXT: br i1 [[C]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4]]<br>
+; UNROLL-NOSIMPLIFY: pred.store.if3:<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION:%.*]] = add i64 [[INDEX]], 1<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* undef, i64 [[INDUCTION]]<br>
; UNROLL-NOSIMPLIFY-NEXT: [[TMP5:%.*]] = load i8, i8* [[TMP4]], align 1<br>
; UNROLL-NOSIMPLIFY-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i32<br>
; UNROLL-NOSIMPLIFY-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i8<br>
; UNROLL-NOSIMPLIFY-NEXT: store i8 [[TMP7]], i8* [[TMP4]], align 1<br>
-; UNROLL-NOSIMPLIFY-NEXT: br label [[PRED_STORE_CONTINUE6]]<br>
-; UNROLL-NOSIMPLIFY: pred.store.continue6:<br>
+; UNROLL-NOSIMPLIFY-NEXT: br label [[PRED_STORE_CONTINUE4]]<br>
+; UNROLL-NOSIMPLIFY: pred.store.continue4:<br>
; UNROLL-NOSIMPLIFY-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2<br>
; UNROLL-NOSIMPLIFY-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], undef<br>
; UNROLL-NOSIMPLIFY-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]<br>
@@ -657,14 +649,12 @@ define void @minimal_bit_widths_with_aliasing_store(i1 %c, i8* %ptr) {<br>
; UNROLL-NOSIMPLIFY: <a href="http://vector.ph" rel="noreferrer" target="_blank">vector.ph</a>:<br>
; UNROLL-NOSIMPLIFY-NEXT: br label [[VECTOR_BODY:%.*]]<br>
; UNROLL-NOSIMPLIFY: vector.body:<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE6:%.*]] ]<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION:%.*]] = add i64 [[INDEX]], 0<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION2:%.*]] = add i64 [[INDEX]], 1<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE4:%.*]] ]<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION:%.*]] = add i64 [[INDEX]], 1<br>
; UNROLL-NOSIMPLIFY-NEXT: [[OFFSET_IDX:%.*]] = sub i64 0, [[INDEX]]<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION3:%.*]] = add i64 [[OFFSET_IDX]], 0<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION4:%.*]] = add i64 [[OFFSET_IDX]], -1<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[TMP0:%.*]] = getelementptr i8, i8* [[PTR:%.*]], i64 [[INDUCTION]]<br>
-; UNROLL-NOSIMPLIFY-NEXT: [[TMP1:%.*]] = getelementptr i8, i8* [[PTR]], i64 [[INDUCTION2]]<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[INDUCTION2:%.*]] = add i64 [[OFFSET_IDX]], -1<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[TMP0:%.*]] = getelementptr i8, i8* [[PTR:%.*]], i64 [[INDEX]]<br>
+; UNROLL-NOSIMPLIFY-NEXT: [[TMP1:%.*]] = getelementptr i8, i8* [[PTR]], i64 [[INDUCTION]]<br>
; UNROLL-NOSIMPLIFY-NEXT: store i8 0, i8* [[TMP0]], align 1<br>
; UNROLL-NOSIMPLIFY-NEXT: store i8 0, i8* [[TMP1]], align 1<br>
; UNROLL-NOSIMPLIFY-NEXT: br i1 [[C:%.*]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]<br>
@@ -675,14 +665,14 @@ define void @minimal_bit_widths_with_aliasing_store(i1 %c, i8* %ptr) {<br>
; UNROLL-NOSIMPLIFY-NEXT: store i8 [[TMP4]], i8* [[TMP0]], align 1<br>
; UNROLL-NOSIMPLIFY-NEXT: br label [[PRED_STORE_CONTINUE]]<br>
; UNROLL-NOSIMPLIFY: pred.store.continue:<br>
-; UNROLL-NOSIMPLIFY-NEXT: br i1 [[C]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6]]<br>
-; UNROLL-NOSIMPLIFY: pred.store.if5:<br>
+; UNROLL-NOSIMPLIFY-NEXT: br i1 [[C]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4]]<br>
+; UNROLL-NOSIMPLIFY: pred.store.if3:<br>
; UNROLL-NOSIMPLIFY-NEXT: [[TMP5:%.*]] = load i8, i8* [[TMP1]], align 1<br>
; UNROLL-NOSIMPLIFY-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i32<br>
; UNROLL-NOSIMPLIFY-NEXT: [[TMP7:%.*]] = trunc i32 [[TMP6]] to i8<br>
; UNROLL-NOSIMPLIFY-NEXT: store i8 [[TMP7]], i8* [[TMP1]], align 1<br>
-; UNROLL-NOSIMPLIFY-NEXT: br label [[PRED_STORE_CONTINUE6]]<br>
-; UNROLL-NOSIMPLIFY: pred.store.continue6:<br>
+; UNROLL-NOSIMPLIFY-NEXT: br label [[PRED_STORE_CONTINUE4]]<br>
+; UNROLL-NOSIMPLIFY: pred.store.continue4:<br>
; UNROLL-NOSIMPLIFY-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2<br>
; UNROLL-NOSIMPLIFY-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 0<br>
; UNROLL-NOSIMPLIFY-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]<br>
<br>
diff --git a/llvm/test/Transforms/LoopVectorize/pointer-induction.ll b/llvm/test/Transforms/LoopVectorize/pointer-induction.ll<br>
index d77ce32e753ee..7a69c80c319c4 100644<br>
--- a/llvm/test/Transforms/LoopVectorize/pointer-induction.ll<br>
+++ b/llvm/test/Transforms/LoopVectorize/pointer-induction.ll<br>
@@ -136,33 +136,31 @@ define void @pointer_induction_used_as_vector(i8** noalias %start.1, i8* noalias<br>
; CHECK: vector.body:<br>
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]<br>
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0<br>
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 0<br>
-; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8*, i8** [[START_1]], i64 [[TMP1]]<br>
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 0<br>
-; CHECK-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, i8* [[START_2]], i64 [[TMP2]]<br>
-; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 1<br>
-; CHECK-NEXT: [[NEXT_GEP5:%.*]] = getelementptr i8, i8* [[START_2]], i64 [[TMP3]]<br>
-; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 2<br>
-; CHECK-NEXT: [[NEXT_GEP6:%.*]] = getelementptr i8, i8* [[START_2]], i64 [[TMP4]]<br>
-; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 3<br>
-; CHECK-NEXT: [[NEXT_GEP7:%.*]] = getelementptr i8, i8* [[START_2]], i64 [[TMP5]]<br>
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i8*> poison, i8* [[NEXT_GEP4]], i32 0<br>
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i8*> [[TMP6]], i8* [[NEXT_GEP5]], i32 1<br>
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i8*> [[TMP7]], i8* [[NEXT_GEP6]], i32 2<br>
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i8*> [[TMP8]], i8* [[NEXT_GEP7]], i32 3<br>
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, <4 x i8*> [[TMP9]], i64 1<br>
-; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8*, i8** [[NEXT_GEP]], i32 0<br>
-; CHECK-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to <4 x i8*>*<br>
-; CHECK-NEXT: store <4 x i8*> [[TMP10]], <4 x i8*>* [[TMP12]], align 8<br>
-; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, i8* [[NEXT_GEP4]], i32 0<br>
-; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP13]] to <4 x i8>*<br>
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, <4 x i8>* [[TMP14]], align 1<br>
-; CHECK-NEXT: [[TMP15:%.*]] = add <4 x i8> [[WIDE_LOAD]], <i8 1, i8 1, i8 1, i8 1><br>
-; CHECK-NEXT: [[TMP16:%.*]] = bitcast i8* [[TMP13]] to <4 x i8>*<br>
-; CHECK-NEXT: store <4 x i8> [[TMP15]], <4 x i8>* [[TMP16]], align 1<br>
+; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8*, i8** [[START_1]], i64 [[INDEX]]<br>
+; CHECK-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, i8* [[START_2]], i64 [[INDEX]]<br>
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1<br>
+; CHECK-NEXT: [[NEXT_GEP5:%.*]] = getelementptr i8, i8* [[START_2]], i64 [[TMP1]]<br>
+; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2<br>
+; CHECK-NEXT: [[NEXT_GEP6:%.*]] = getelementptr i8, i8* [[START_2]], i64 [[TMP2]]<br>
+; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3<br>
+; CHECK-NEXT: [[NEXT_GEP7:%.*]] = getelementptr i8, i8* [[START_2]], i64 [[TMP3]]<br>
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i8*> poison, i8* [[NEXT_GEP4]], i32 0<br>
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i8*> [[TMP4]], i8* [[NEXT_GEP5]], i32 1<br>
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i8*> [[TMP5]], i8* [[NEXT_GEP6]], i32 2<br>
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i8*> [[TMP6]], i8* [[NEXT_GEP7]], i32 3<br>
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, <4 x i8*> [[TMP7]], i64 1<br>
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8*, i8** [[NEXT_GEP]], i32 0<br>
+; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to <4 x i8*>*<br>
+; CHECK-NEXT: store <4 x i8*> [[TMP8]], <4 x i8*>* [[TMP10]], align 8<br>
+; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, i8* [[NEXT_GEP4]], i32 0<br>
+; CHECK-NEXT: [[TMP12:%.*]] = bitcast i8* [[TMP11]] to <4 x i8>*<br>
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, <4 x i8>* [[TMP12]], align 1<br>
+; CHECK-NEXT: [[TMP13:%.*]] = add <4 x i8> [[WIDE_LOAD]], <i8 1, i8 1, i8 1, i8 1><br>
+; CHECK-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP11]] to <4 x i8>*<br>
+; CHECK-NEXT: store <4 x i8> [[TMP13]], <4 x i8>* [[TMP14]], align 1<br>
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4<br>
-; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]<br>
-; CHECK-NEXT: br i1 [[TMP17]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]<br>
+; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]<br>
+; CHECK-NEXT: br i1 [[TMP15]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]<br>
; CHECK: middle.block:<br>
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]<br>
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]<br>
<br>
diff --git a/llvm/test/Transforms/LoopVectorize/pr30654-phiscev-sext-trunc.ll b/llvm/test/Transforms/LoopVectorize/pr30654-phiscev-sext-trunc.ll<br>
index 242e41195e841..238ba6ccc63db 100644<br>
--- a/llvm/test/Transforms/LoopVectorize/pr30654-phiscev-sext-trunc.ll<br>
+++ b/llvm/test/Transforms/LoopVectorize/pr30654-phiscev-sext-trunc.ll<br>
@@ -51,20 +51,19 @@ define void @doit1(i32 %n, i32 %step) local_unnamed_addr {<br>
; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[TMP4]], i8 [[TMP5]])<br>
; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i8, i1 } [[MUL]], 0<br>
; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i8, i1 } [[MUL]], 1<br>
-; CHECK-NEXT: [[TMP6:%.*]] = add i8 [[MUL_RESULT]], 0<br>
-; CHECK-NEXT: [[TMP7:%.*]] = sub i8 0, [[MUL_RESULT]]<br>
-; CHECK-NEXT: [[TMP8:%.*]] = icmp sgt i8 [[TMP7]], 0<br>
-; CHECK-NEXT: [[TMP9:%.*]] = icmp slt i8 [[TMP6]], 0<br>
-; CHECK-NEXT: [[TMP10:%.*]] = select i1 [[TMP3]], i1 [[TMP8]], i1 [[TMP9]]<br>
-; CHECK-NEXT: [[TMP11:%.*]] = icmp ugt i64 [[TMP0]], 255<br>
-; CHECK-NEXT: [[TMP12:%.*]] = icmp ne i8 [[TMP1]], 0<br>
-; CHECK-NEXT: [[TMP13:%.*]] = and i1 [[TMP11]], [[TMP12]]<br>
-; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP10]], [[TMP13]]<br>
-; CHECK-NEXT: [[TMP15:%.*]] = or i1 [[TMP14]], [[MUL_OVERFLOW]]<br>
-; CHECK-NEXT: [[TMP16:%.*]] = sext i8 [[TMP1]] to i32<br>
-; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[STEP]], [[TMP16]]<br>
-; CHECK-NEXT: [[TMP17:%.*]] = or i1 [[TMP15]], [[IDENT_CHECK]]<br>
-; CHECK-NEXT: br i1 [[TMP17]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]<br>
+; CHECK-NEXT: [[TMP6:%.*]] = sub i8 0, [[MUL_RESULT]]<br>
+; CHECK-NEXT: [[TMP7:%.*]] = icmp sgt i8 [[TMP6]], 0<br>
+; CHECK-NEXT: [[TMP8:%.*]] = icmp slt i8 [[MUL_RESULT]], 0<br>
+; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP3]], i1 [[TMP7]], i1 [[TMP8]]<br>
+; CHECK-NEXT: [[TMP10:%.*]] = icmp ugt i64 [[TMP0]], 255<br>
+; CHECK-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP1]], 0<br>
+; CHECK-NEXT: [[TMP12:%.*]] = and i1 [[TMP10]], [[TMP11]]<br>
+; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP9]], [[TMP12]]<br>
+; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP13]], [[MUL_OVERFLOW]]<br>
+; CHECK-NEXT: [[TMP15:%.*]] = sext i8 [[TMP1]] to i32<br>
+; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[STEP]], [[TMP15]]<br>
+; CHECK-NEXT: [[TMP16:%.*]] = or i1 [[TMP14]], [[IDENT_CHECK]]<br>
+; CHECK-NEXT: br i1 [[TMP16]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]<br>
; CHECK: <a href="http://vector.ph" rel="noreferrer" target="_blank">vector.ph</a>:<br>
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[WIDE_TRIP_COUNT]], 4<br>
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[N_MOD_VF]]<br>
@@ -72,24 +71,24 @@ define void @doit1(i32 %n, i32 %step) local_unnamed_addr {<br>
; CHECK-NEXT: [[IND_END:%.*]] = mul i32 [[CAST_CRD]], [[STEP]]<br>
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[STEP]], i32 0<br>
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer<br>
-; CHECK-NEXT: [[TMP18:%.*]] = mul <4 x i32> <i32 0, i32 1, i32 2, i32 3>, [[DOTSPLAT]]<br>
-; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> [[TMP18]], zeroinitializer<br>
-; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[STEP]], 4<br>
-; CHECK-NEXT: [[DOTSPLATINSERT2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP19]], i32 0<br>
+; CHECK-NEXT: [[TMP17:%.*]] = mul <4 x i32> <i32 0, i32 1, i32 2, i32 3>, [[DOTSPLAT]]<br>
+; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> [[TMP17]], zeroinitializer<br>
+; CHECK-NEXT: [[TMP18:%.*]] = mul i32 [[STEP]], 4<br>
+; CHECK-NEXT: [[DOTSPLATINSERT2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP18]], i32 0<br>
; CHECK-NEXT: [[DOTSPLAT3:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT2]], <4 x i32> poison, <4 x i32> zeroinitializer<br>
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]<br>
; CHECK: vector.body:<br>
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]<br>
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ [[INDUCTION]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]<br>
-; CHECK-NEXT: [[TMP20:%.*]] = add i64 [[INDEX]], 0<br>
-; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [250 x i32], [250 x i32]* @a, i64 0, i64 [[TMP20]]<br>
-; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i32, i32* [[TMP21]], i32 0<br>
-; CHECK-NEXT: [[TMP23:%.*]] = bitcast i32* [[TMP22]] to <4 x i32>*<br>
-; CHECK-NEXT: store <4 x i32> [[VEC_IND]], <4 x i32>* [[TMP23]], align 4<br>
+; CHECK-NEXT: [[TMP19:%.*]] = add i64 [[INDEX]], 0<br>
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [250 x i32], [250 x i32]* @a, i64 0, i64 [[TMP19]]<br>
+; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i32 0<br>
+; CHECK-NEXT: [[TMP22:%.*]] = bitcast i32* [[TMP21]] to <4 x i32>*<br>
+; CHECK-NEXT: store <4 x i32> [[VEC_IND]], <4 x i32>* [[TMP22]], align 4<br>
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4<br>
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], [[DOTSPLAT3]]<br>
-; CHECK-NEXT: [[TMP24:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]<br>
-; CHECK-NEXT: br i1 [[TMP24]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]<br>
+; CHECK-NEXT: [[TMP23:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]<br>
+; CHECK-NEXT: br i1 [[TMP23]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]<br>
; CHECK: middle.block:<br>
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[WIDE_TRIP_COUNT]], [[N_VEC]]<br>
; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_END_LOOPEXIT:%.*]], label [[SCALAR_PH]]<br>
@@ -177,20 +176,19 @@ define void @doit2(i32 %n, i32 %step) local_unnamed_addr {<br>
; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[TMP4]], i8 [[TMP5]])<br>
; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i8, i1 } [[MUL]], 0<br>
; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i8, i1 } [[MUL]], 1<br>
-; CHECK-NEXT: [[TMP6:%.*]] = add i8 [[MUL_RESULT]], 0<br>
-; CHECK-NEXT: [[TMP7:%.*]] = sub i8 0, [[MUL_RESULT]]<br>
-; CHECK-NEXT: [[TMP8:%.*]] = icmp ugt i8 [[TMP7]], 0<br>
-; CHECK-NEXT: [[TMP9:%.*]] = icmp ult i8 [[TMP6]], 0<br>
-; CHECK-NEXT: [[TMP10:%.*]] = select i1 [[TMP3]], i1 [[TMP8]], i1 [[TMP9]]<br>
-; CHECK-NEXT: [[TMP11:%.*]] = icmp ugt i64 [[TMP0]], 255<br>
-; CHECK-NEXT: [[TMP12:%.*]] = icmp ne i8 [[TMP1]], 0<br>
-; CHECK-NEXT: [[TMP13:%.*]] = and i1 [[TMP11]], [[TMP12]]<br>
-; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP10]], [[TMP13]]<br>
-; CHECK-NEXT: [[TMP15:%.*]] = or i1 [[TMP14]], [[MUL_OVERFLOW]]<br>
-; CHECK-NEXT: [[TMP16:%.*]] = sext i8 [[TMP1]] to i32<br>
-; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[STEP]], [[TMP16]]<br>
-; CHECK-NEXT: [[TMP17:%.*]] = or i1 [[TMP15]], [[IDENT_CHECK]]<br>
-; CHECK-NEXT: br i1 [[TMP17]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]<br>
+; CHECK-NEXT: [[TMP6:%.*]] = sub i8 0, [[MUL_RESULT]]<br>
+; CHECK-NEXT: [[TMP7:%.*]] = icmp ugt i8 [[TMP6]], 0<br>
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ult i8 [[MUL_RESULT]], 0<br>
+; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP3]], i1 [[TMP7]], i1 [[TMP8]]<br>
+; CHECK-NEXT: [[TMP10:%.*]] = icmp ugt i64 [[TMP0]], 255<br>
+; CHECK-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP1]], 0<br>
+; CHECK-NEXT: [[TMP12:%.*]] = and i1 [[TMP10]], [[TMP11]]<br>
+; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP9]], [[TMP12]]<br>
+; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP13]], [[MUL_OVERFLOW]]<br>
+; CHECK-NEXT: [[TMP15:%.*]] = sext i8 [[TMP1]] to i32<br>
+; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[STEP]], [[TMP15]]<br>
+; CHECK-NEXT: [[TMP16:%.*]] = or i1 [[TMP14]], [[IDENT_CHECK]]<br>
+; CHECK-NEXT: br i1 [[TMP16]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]<br>
; CHECK: <a href="http://vector.ph" rel="noreferrer" target="_blank">vector.ph</a>:<br>
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[WIDE_TRIP_COUNT]], 4<br>
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[N_MOD_VF]]<br>
@@ -198,24 +196,24 @@ define void @doit2(i32 %n, i32 %step) local_unnamed_addr {<br>
; CHECK-NEXT: [[IND_END:%.*]] = mul i32 [[CAST_CRD]], [[STEP]]<br>
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[STEP]], i32 0<br>
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer<br>
-; CHECK-NEXT: [[TMP18:%.*]] = mul <4 x i32> <i32 0, i32 1, i32 2, i32 3>, [[DOTSPLAT]]<br>
-; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> [[TMP18]], zeroinitializer<br>
-; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[STEP]], 4<br>
-; CHECK-NEXT: [[DOTSPLATINSERT2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP19]], i32 0<br>
+; CHECK-NEXT: [[TMP17:%.*]] = mul <4 x i32> <i32 0, i32 1, i32 2, i32 3>, [[DOTSPLAT]]<br>
+; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> [[TMP17]], zeroinitializer<br>
+; CHECK-NEXT: [[TMP18:%.*]] = mul i32 [[STEP]], 4<br>
+; CHECK-NEXT: [[DOTSPLATINSERT2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP18]], i32 0<br>
; CHECK-NEXT: [[DOTSPLAT3:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT2]], <4 x i32> poison, <4 x i32> zeroinitializer<br>
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]<br>
; CHECK: vector.body:<br>
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]<br>
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ [[INDUCTION]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]<br>
-; CHECK-NEXT: [[TMP20:%.*]] = add i64 [[INDEX]], 0<br>
-; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [250 x i32], [250 x i32]* @a, i64 0, i64 [[TMP20]]<br>
-; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i32, i32* [[TMP21]], i32 0<br>
-; CHECK-NEXT: [[TMP23:%.*]] = bitcast i32* [[TMP22]] to <4 x i32>*<br>
-; CHECK-NEXT: store <4 x i32> [[VEC_IND]], <4 x i32>* [[TMP23]], align 4<br>
+; CHECK-NEXT: [[TMP19:%.*]] = add i64 [[INDEX]], 0<br>
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [250 x i32], [250 x i32]* @a, i64 0, i64 [[TMP19]]<br>
+; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i32 0<br>
+; CHECK-NEXT: [[TMP22:%.*]] = bitcast i32* [[TMP21]] to <4 x i32>*<br>
+; CHECK-NEXT: store <4 x i32> [[VEC_IND]], <4 x i32>* [[TMP22]], align 4<br>
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4<br>
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], [[DOTSPLAT3]]<br>
-; CHECK-NEXT: [[TMP24:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]<br>
-; CHECK-NEXT: br i1 [[TMP24]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]<br>
+; CHECK-NEXT: [[TMP23:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]<br>
+; CHECK-NEXT: br i1 [[TMP23]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]<br>
; CHECK: middle.block:<br>
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[WIDE_TRIP_COUNT]], [[N_VEC]]<br>
; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_END_LOOPEXIT:%.*]], label [[SCALAR_PH]]<br>
@@ -377,17 +375,16 @@ define void @doit4(i32 %n, i8 signext %cstep) local_unnamed_addr {<br>
; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[TMP3]], i8 [[TMP4]])<br>
; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i8, i1 } [[MUL]], 0<br>
; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i8, i1 } [[MUL]], 1<br>
-; CHECK-NEXT: [[TMP5:%.*]] = add i8 [[MUL_RESULT]], 0<br>
-; CHECK-NEXT: [[TMP6:%.*]] = sub i8 0, [[MUL_RESULT]]<br>
-; CHECK-NEXT: [[TMP7:%.*]] = icmp sgt i8 [[TMP6]], 0<br>
-; CHECK-NEXT: [[TMP8:%.*]] = icmp slt i8 [[TMP5]], 0<br>
-; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP2]], i1 [[TMP7]], i1 [[TMP8]]<br>
-; CHECK-NEXT: [[TMP10:%.*]] = icmp ugt i64 [[TMP0]], 255<br>
-; CHECK-NEXT: [[TMP11:%.*]] = icmp ne i8 [[CSTEP]], 0<br>
-; CHECK-NEXT: [[TMP12:%.*]] = and i1 [[TMP10]], [[TMP11]]<br>
-; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP9]], [[TMP12]]<br>
-; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP13]], [[MUL_OVERFLOW]]<br>
-; CHECK-NEXT: br i1 [[TMP14]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]<br>
+; CHECK-NEXT: [[TMP5:%.*]] = sub i8 0, [[MUL_RESULT]]<br>
+; CHECK-NEXT: [[TMP6:%.*]] = icmp sgt i8 [[TMP5]], 0<br>
+; CHECK-NEXT: [[TMP7:%.*]] = icmp slt i8 [[MUL_RESULT]], 0<br>
+; CHECK-NEXT: [[TMP8:%.*]] = select i1 [[TMP2]], i1 [[TMP6]], i1 [[TMP7]]<br>
+; CHECK-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[TMP0]], 255<br>
+; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i8 [[CSTEP]], 0<br>
+; CHECK-NEXT: [[TMP11:%.*]] = and i1 [[TMP9]], [[TMP10]]<br>
+; CHECK-NEXT: [[TMP12:%.*]] = or i1 [[TMP8]], [[TMP11]]<br>
+; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP12]], [[MUL_OVERFLOW]]<br>
+; CHECK-NEXT: br i1 [[TMP13]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]<br>
; CHECK: <a href="http://vector.ph" rel="noreferrer" target="_blank">vector.ph</a>:<br>
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[WIDE_TRIP_COUNT]], 4<br>
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[N_MOD_VF]]<br>
@@ -395,24 +392,24 @@ define void @doit4(i32 %n, i8 signext %cstep) local_unnamed_addr {<br>
; CHECK-NEXT: [[IND_END:%.*]] = mul i32 [[CAST_CRD]], [[CONV]]<br>
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[CONV]], i32 0<br>
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer<br>
-; CHECK-NEXT: [[TMP15:%.*]] = mul <4 x i32> <i32 0, i32 1, i32 2, i32 3>, [[DOTSPLAT]]<br>
-; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> [[TMP15]], zeroinitializer<br>
-; CHECK-NEXT: [[TMP16:%.*]] = mul i32 [[CONV]], 4<br>
-; CHECK-NEXT: [[DOTSPLATINSERT2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP16]], i32 0<br>
+; CHECK-NEXT: [[TMP14:%.*]] = mul <4 x i32> <i32 0, i32 1, i32 2, i32 3>, [[DOTSPLAT]]<br>
+; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> [[TMP14]], zeroinitializer<br>
+; CHECK-NEXT: [[TMP15:%.*]] = mul i32 [[CONV]], 4<br>
+; CHECK-NEXT: [[DOTSPLATINSERT2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP15]], i32 0<br>
; CHECK-NEXT: [[DOTSPLAT3:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT2]], <4 x i32> poison, <4 x i32> zeroinitializer<br>
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]<br>
; CHECK: vector.body:<br>
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]<br>
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ [[INDUCTION]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]<br>
-; CHECK-NEXT: [[TMP17:%.*]] = add i64 [[INDEX]], 0<br>
-; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [250 x i32], [250 x i32]* @a, i64 0, i64 [[TMP17]]<br>
-; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, i32* [[TMP18]], i32 0<br>
-; CHECK-NEXT: [[TMP20:%.*]] = bitcast i32* [[TMP19]] to <4 x i32>*<br>
-; CHECK-NEXT: store <4 x i32> [[VEC_IND]], <4 x i32>* [[TMP20]], align 4<br>
+; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[INDEX]], 0<br>
+; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [250 x i32], [250 x i32]* @a, i64 0, i64 [[TMP16]]<br>
+; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i32 0<br>
+; CHECK-NEXT: [[TMP19:%.*]] = bitcast i32* [[TMP18]] to <4 x i32>*<br>
+; CHECK-NEXT: store <4 x i32> [[VEC_IND]], <4 x i32>* [[TMP19]], align 4<br>
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4<br>
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], [[DOTSPLAT3]]<br>
-; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]<br>
-; CHECK-NEXT: br i1 [[TMP21]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]<br>
+; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]<br>
+; CHECK-NEXT: br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]<br>
; CHECK: middle.block:<br>
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[WIDE_TRIP_COUNT]], [[N_VEC]]<br>
; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_END_LOOPEXIT:%.*]], label [[SCALAR_PH]]<br>
<br>
diff --git a/llvm/test/Transforms/LoopVectorize/pr45679-fold-tail-by-masking.ll b/llvm/test/Transforms/LoopVectorize/pr45679-fold-tail-by-masking.ll<br>
index d77abbd39f0d2..3780b3888a80c 100644<br>
--- a/llvm/test/Transforms/LoopVectorize/pr45679-fold-tail-by-masking.ll<br>
+++ b/llvm/test/Transforms/LoopVectorize/pr45679-fold-tail-by-masking.ll<br>
@@ -55,7 +55,7 @@ define void @pr45679(i32* %A) optsize {<br>
; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4<br>
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], <i32 4, i32 4, i32 4, i32 4><br>
; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i32 [[INDEX_NEXT]], 16<br>
-; CHECK-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !0<br>
+; CHECK-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]<br>
; CHECK: middle.block:<br>
; CHECK-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]]<br>
; CHECK: <a href="http://scalar.ph" rel="noreferrer" target="_blank">scalar.ph</a>:<br>
@@ -67,7 +67,7 @@ define void @pr45679(i32* %A) optsize {<br>
; CHECK-NEXT: store i32 13, i32* [[ARRAYIDX]], align 1<br>
; CHECK-NEXT: [[RIVPLUS1]] = add nuw nsw i32 [[RIV]], 1<br>
; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[RIVPLUS1]], 14<br>
-; CHECK-NEXT: br i1 [[COND]], label [[EXIT]], label [[LOOP]], !llvm.loop !2<br>
+; CHECK-NEXT: br i1 [[COND]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP2:![0-9]+]]<br>
; CHECK: exit:<br>
; CHECK-NEXT: ret void<br>
;<br>
@@ -117,7 +117,7 @@ define void @pr45679(i32* %A) optsize {<br>
; VF2UF2-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4<br>
; VF2UF2-NEXT: [[VEC_IND_NEXT]] = add <2 x i32> [[STEP_ADD]], <i32 2, i32 2><br>
; VF2UF2-NEXT: [[TMP14:%.*]] = icmp eq i32 [[INDEX_NEXT]], 16<br>
-; VF2UF2-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !0<br>
+; VF2UF2-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]<br>
; VF2UF2: middle.block:<br>
; VF2UF2-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]]<br>
; VF2UF2: <a href="http://scalar.ph" rel="noreferrer" target="_blank">scalar.ph</a>:<br>
@@ -129,7 +129,7 @@ define void @pr45679(i32* %A) optsize {<br>
; VF2UF2-NEXT: store i32 13, i32* [[ARRAYIDX]], align 1<br>
; VF2UF2-NEXT: [[RIVPLUS1]] = add nuw nsw i32 [[RIV]], 1<br>
; VF2UF2-NEXT: [[COND:%.*]] = icmp eq i32 [[RIVPLUS1]], 14<br>
-; VF2UF2-NEXT: br i1 [[COND]], label [[EXIT]], label [[LOOP]], !llvm.loop !2<br>
+; VF2UF2-NEXT: br i1 [[COND]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP2:![0-9]+]]<br>
; VF2UF2: exit:<br>
; VF2UF2-NEXT: ret void<br>
;<br>
@@ -139,42 +139,41 @@ define void @pr45679(i32* %A) optsize {<br>
; VF1UF4: <a href="http://vector.ph" rel="noreferrer" target="_blank">vector.ph</a>:<br>
; VF1UF4-NEXT: br label [[VECTOR_BODY:%.*]]<br>
; VF1UF4: vector.body:<br>
-; VF1UF4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE9:%.*]] ]<br>
-; VF1UF4-NEXT: [[INDUCTION:%.*]] = add i32 [[INDEX]], 0<br>
-; VF1UF4-NEXT: [[INDUCTION1:%.*]] = add i32 [[INDEX]], 1<br>
-; VF1UF4-NEXT: [[INDUCTION2:%.*]] = add i32 [[INDEX]], 2<br>
-; VF1UF4-NEXT: [[INDUCTION3:%.*]] = add i32 [[INDEX]], 3<br>
-; VF1UF4-NEXT: [[TMP0:%.*]] = icmp ule i32 [[INDUCTION]], 13<br>
-; VF1UF4-NEXT: [[TMP1:%.*]] = icmp ule i32 [[INDUCTION1]], 13<br>
-; VF1UF4-NEXT: [[TMP2:%.*]] = icmp ule i32 [[INDUCTION2]], 13<br>
-; VF1UF4-NEXT: [[TMP3:%.*]] = icmp ule i32 [[INDUCTION3]], 13<br>
+; VF1UF4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE8:%.*]] ]<br>
+; VF1UF4-NEXT: [[INDUCTION:%.*]] = add i32 [[INDEX]], 1<br>
+; VF1UF4-NEXT: [[INDUCTION1:%.*]] = add i32 [[INDEX]], 2<br>
+; VF1UF4-NEXT: [[INDUCTION2:%.*]] = add i32 [[INDEX]], 3<br>
+; VF1UF4-NEXT: [[TMP0:%.*]] = icmp ule i32 [[INDEX]], 13<br>
+; VF1UF4-NEXT: [[TMP1:%.*]] = icmp ule i32 [[INDUCTION]], 13<br>
+; VF1UF4-NEXT: [[TMP2:%.*]] = icmp ule i32 [[INDUCTION1]], 13<br>
+; VF1UF4-NEXT: [[TMP3:%.*]] = icmp ule i32 [[INDUCTION2]], 13<br>
; VF1UF4-NEXT: br i1 [[TMP0]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]<br>
; VF1UF4: pred.store.if:<br>
-; VF1UF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i32 [[INDUCTION]]<br>
+; VF1UF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i32 [[INDEX]]<br>
; VF1UF4-NEXT: store i32 13, i32* [[TMP4]], align 1<br>
; VF1UF4-NEXT: br label [[PRED_STORE_CONTINUE]]<br>
; VF1UF4: pred.store.continue:<br>
-; VF1UF4-NEXT: br i1 [[TMP1]], label [[PRED_STORE_IF4:%.*]], label [[PRED_STORE_CONTINUE5:%.*]]<br>
-; VF1UF4: pred.store.if4:<br>
-; VF1UF4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[INDUCTION1]]<br>
+; VF1UF4-NEXT: br i1 [[TMP1]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]]<br>
+; VF1UF4: pred.store.if3:<br>
+; VF1UF4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[INDUCTION]]<br>
; VF1UF4-NEXT: store i32 13, i32* [[TMP5]], align 1<br>
-; VF1UF4-NEXT: br label [[PRED_STORE_CONTINUE5]]<br>
-; VF1UF4: pred.store.continue5:<br>
-; VF1UF4-NEXT: br i1 [[TMP2]], label [[PRED_STORE_IF6:%.*]], label [[PRED_STORE_CONTINUE7:%.*]]<br>
-; VF1UF4: pred.store.if6:<br>
-; VF1UF4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[INDUCTION2]]<br>
+; VF1UF4-NEXT: br label [[PRED_STORE_CONTINUE4]]<br>
+; VF1UF4: pred.store.continue4:<br>
+; VF1UF4-NEXT: br i1 [[TMP2]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6:%.*]]<br>
+; VF1UF4: pred.store.if5:<br>
+; VF1UF4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[INDUCTION1]]<br>
; VF1UF4-NEXT: store i32 13, i32* [[TMP6]], align 1<br>
-; VF1UF4-NEXT: br label [[PRED_STORE_CONTINUE7]]<br>
-; VF1UF4: pred.store.continue7:<br>
-; VF1UF4-NEXT: br i1 [[TMP3]], label [[PRED_STORE_IF8:%.*]], label [[PRED_STORE_CONTINUE9]]<br>
-; VF1UF4: pred.store.if8:<br>
-; VF1UF4-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[INDUCTION3]]<br>
+; VF1UF4-NEXT: br label [[PRED_STORE_CONTINUE6]]<br>
+; VF1UF4: pred.store.continue6:<br>
+; VF1UF4-NEXT: br i1 [[TMP3]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8]]<br>
+; VF1UF4: pred.store.if7:<br>
+; VF1UF4-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[INDUCTION2]]<br>
; VF1UF4-NEXT: store i32 13, i32* [[TMP7]], align 1<br>
-; VF1UF4-NEXT: br label [[PRED_STORE_CONTINUE9]]<br>
-; VF1UF4: pred.store.continue9:<br>
+; VF1UF4-NEXT: br label [[PRED_STORE_CONTINUE8]]<br>
+; VF1UF4: pred.store.continue8:<br>
; VF1UF4-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4<br>
; VF1UF4-NEXT: [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], 16<br>
-; VF1UF4-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]]<br>
+; VF1UF4-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]<br>
; VF1UF4: middle.block:<br>
; VF1UF4-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]]<br>
; VF1UF4: <a href="http://scalar.ph" rel="noreferrer" target="_blank">scalar.ph</a>:<br>
@@ -186,7 +185,7 @@ define void @pr45679(i32* %A) optsize {<br>
; VF1UF4-NEXT: store i32 13, i32* [[ARRAYIDX]], align 1<br>
; VF1UF4-NEXT: [[RIVPLUS1]] = add nuw nsw i32 [[RIV]], 1<br>
; VF1UF4-NEXT: [[COND:%.*]] = icmp eq i32 [[RIVPLUS1]], 14<br>
-; VF1UF4-NEXT: br i1 [[COND]], label [[EXIT]], label [[LOOP]]<br>
+; VF1UF4-NEXT: br i1 [[COND]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP2:![0-9]+]]<br>
; VF1UF4: exit:<br>
; VF1UF4-NEXT: ret void<br>
;<br>
<br>
diff --git a/llvm/test/Transforms/LoopVectorize/runtime-check-small-clamped-bounds.ll b/llvm/test/Transforms/LoopVectorize/runtime-check-small-clamped-bounds.ll<br>
index 8f7a3a6bd41ad..adb22dc56b910 100644<br>
--- a/llvm/test/Transforms/LoopVectorize/runtime-check-small-clamped-bounds.ll<br>
+++ b/llvm/test/Transforms/LoopVectorize/runtime-check-small-clamped-bounds.ll<br>
@@ -20,20 +20,19 @@ define void @load_clamped_index(i32* %A, i32* %B, i32 %N) {<br>
; CHECK: vector.scevcheck:<br>
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1<br>
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i2<br>
-; CHECK-NEXT: [[TMP2:%.*]] = add i2 [[TMP1]], 0<br>
-; CHECK-NEXT: [[TMP3:%.*]] = sub i2 0, [[TMP1]]<br>
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt i2 [[TMP3]], 0<br>
-; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i2 [[TMP2]], 0<br>
-; CHECK-NEXT: [[TMP6:%.*]] = icmp ugt i32 [[TMP0]], 3<br>
-; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]<br>
-; CHECK-NEXT: br i1 [[TMP7]], label [[SCALAR_PH]], label [[VECTOR_MEMCHECK:%.*]]<br>
+; CHECK-NEXT: [[TMP2:%.*]] = sub i2 0, [[TMP1]]<br>
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i2 [[TMP2]], 0<br>
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i2 [[TMP1]], 0<br>
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ugt i32 [[TMP0]], 3<br>
+; CHECK-NEXT: [[TMP6:%.*]] = or i1 [[TMP4]], [[TMP5]]<br>
+; CHECK-NEXT: br i1 [[TMP6]], label [[SCALAR_PH]], label [[VECTOR_MEMCHECK:%.*]]<br>
; CHECK: vector.memcheck:<br>
-; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[N]], -1<br>
-; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64<br>
-; CHECK-NEXT: [[TMP10:%.*]] = add nuw nsw i64 [[TMP9]], 1<br>
-; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i32, i32* [[B]], i64 [[TMP10]]<br>
+; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[N]], -1<br>
+; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64<br>
+; CHECK-NEXT: [[TMP9:%.*]] = add nuw nsw i64 [[TMP8]], 1<br>
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i32, i32* [[B]], i64 [[TMP9]]<br>
; CHECK-NEXT: [[SCEVGEP2:%.*]] = bitcast i32* [[SCEVGEP]] to i8*<br>
-; CHECK-NEXT: [[SCEVGEP4:%.*]] = getelementptr i32, i32* [[A]], i64 [[TMP10]]<br>
+; CHECK-NEXT: [[SCEVGEP4:%.*]] = getelementptr i32, i32* [[A]], i64 [[TMP9]]<br>
; CHECK-NEXT: [[SCEVGEP45:%.*]] = bitcast i32* [[SCEVGEP4]] to i8*<br>
; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult i8* [[B1]], [[SCEVGEP45]]<br>
; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult i8* [[A3]], [[SCEVGEP2]]<br>
@@ -45,20 +44,20 @@ define void @load_clamped_index(i32* %A, i32* %B, i32 %N) {<br>
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]<br>
; CHECK: vector.body:<br>
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]<br>
-; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[INDEX]], 0<br>
-; CHECK-NEXT: [[TMP12:%.*]] = urem i32 [[TMP11]], 4<br>
-; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[TMP12]]<br>
-; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, i32* [[TMP13]], i32 0<br>
-; CHECK-NEXT: [[TMP15:%.*]] = bitcast i32* [[TMP14]] to <2 x i32>*<br>
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, <2 x i32>* [[TMP15]], align 4, !alias.scope !0<br>
-; CHECK-NEXT: [[TMP16:%.*]] = add <2 x i32> [[WIDE_LOAD]], <i32 10, i32 10><br>
-; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, i32* [[B]], i32 [[TMP11]]<br>
-; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i32 0<br>
-; CHECK-NEXT: [[TMP19:%.*]] = bitcast i32* [[TMP18]] to <2 x i32>*<br>
-; CHECK-NEXT: store <2 x i32> [[TMP16]], <2 x i32>* [[TMP19]], align 4, !alias.scope !3, !noalias !0<br>
+; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[INDEX]], 0<br>
+; CHECK-NEXT: [[TMP11:%.*]] = urem i32 [[TMP10]], 4<br>
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[TMP11]]<br>
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, i32* [[TMP12]], i32 0<br>
+; CHECK-NEXT: [[TMP14:%.*]] = bitcast i32* [[TMP13]] to <2 x i32>*<br>
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, <2 x i32>* [[TMP14]], align 4, !alias.scope !0<br>
+; CHECK-NEXT: [[TMP15:%.*]] = add <2 x i32> [[WIDE_LOAD]], <i32 10, i32 10><br>
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, i32* [[B]], i32 [[TMP10]]<br>
+; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, i32* [[TMP16]], i32 0<br>
+; CHECK-NEXT: [[TMP18:%.*]] = bitcast i32* [[TMP17]] to <2 x i32>*<br>
+; CHECK-NEXT: store <2 x i32> [[TMP15]], <2 x i32>* [[TMP18]], align 4, !alias.scope !3, !noalias !0<br>
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2<br>
-; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]<br>
-; CHECK-NEXT: br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]<br>
+; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]<br>
+; CHECK-NEXT: br i1 [[TMP19]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]<br>
; CHECK: middle.block:<br>
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]<br>
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]<br>
@@ -109,20 +108,19 @@ define void @store_clamped_index(i32* %A, i32* %B, i32 %N) {<br>
; CHECK: vector.scevcheck:<br>
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1<br>
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i2<br>
-; CHECK-NEXT: [[TMP2:%.*]] = add i2 [[TMP1]], 0<br>
-; CHECK-NEXT: [[TMP3:%.*]] = sub i2 0, [[TMP1]]<br>
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt i2 [[TMP3]], 0<br>
-; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i2 [[TMP2]], 0<br>
-; CHECK-NEXT: [[TMP6:%.*]] = icmp ugt i32 [[TMP0]], 3<br>
-; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]<br>
-; CHECK-NEXT: br i1 [[TMP7]], label [[SCALAR_PH]], label [[VECTOR_MEMCHECK:%.*]]<br>
+; CHECK-NEXT: [[TMP2:%.*]] = sub i2 0, [[TMP1]]<br>
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i2 [[TMP2]], 0<br>
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i2 [[TMP1]], 0<br>
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ugt i32 [[TMP0]], 3<br>
+; CHECK-NEXT: [[TMP6:%.*]] = or i1 [[TMP4]], [[TMP5]]<br>
+; CHECK-NEXT: br i1 [[TMP6]], label [[SCALAR_PH]], label [[VECTOR_MEMCHECK:%.*]]<br>
; CHECK: vector.memcheck:<br>
-; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[N]], -1<br>
-; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64<br>
-; CHECK-NEXT: [[TMP10:%.*]] = add nuw nsw i64 [[TMP9]], 1<br>
-; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i32, i32* [[B]], i64 [[TMP10]]<br>
+; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[N]], -1<br>
+; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64<br>
+; CHECK-NEXT: [[TMP9:%.*]] = add nuw nsw i64 [[TMP8]], 1<br>
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i32, i32* [[B]], i64 [[TMP9]]<br>
; CHECK-NEXT: [[SCEVGEP2:%.*]] = bitcast i32* [[SCEVGEP]] to i8*<br>
-; CHECK-NEXT: [[SCEVGEP4:%.*]] = getelementptr i32, i32* [[A]], i64 [[TMP10]]<br>
+; CHECK-NEXT: [[SCEVGEP4:%.*]] = getelementptr i32, i32* [[A]], i64 [[TMP9]]<br>
; CHECK-NEXT: [[SCEVGEP45:%.*]] = bitcast i32* [[SCEVGEP4]] to i8*<br>
; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult i8* [[B1]], [[SCEVGEP45]]<br>
; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult i8* [[A3]], [[SCEVGEP2]]<br>
@@ -134,20 +132,20 @@ define void @store_clamped_index(i32* %A, i32* %B, i32 %N) {<br>
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]<br>
; CHECK: vector.body:<br>
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]<br>
-; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[INDEX]], 0<br>
-; CHECK-NEXT: [[TMP12:%.*]] = urem i32 [[TMP11]], 4<br>
-; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, i32* [[B]], i32 [[TMP11]]<br>
-; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, i32* [[TMP13]], i32 0<br>
-; CHECK-NEXT: [[TMP15:%.*]] = bitcast i32* [[TMP14]] to <2 x i32>*<br>
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, <2 x i32>* [[TMP15]], align 4, !alias.scope !8, !noalias !11<br>
-; CHECK-NEXT: [[TMP16:%.*]] = add <2 x i32> [[WIDE_LOAD]], <i32 10, i32 10><br>
-; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[TMP12]]<br>
-; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i32 0<br>
-; CHECK-NEXT: [[TMP19:%.*]] = bitcast i32* [[TMP18]] to <2 x i32>*<br>
-; CHECK-NEXT: store <2 x i32> [[TMP16]], <2 x i32>* [[TMP19]], align 4, !alias.scope !11<br>
+; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[INDEX]], 0<br>
+; CHECK-NEXT: [[TMP11:%.*]] = urem i32 [[TMP10]], 4<br>
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, i32* [[B]], i32 [[TMP10]]<br>
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, i32* [[TMP12]], i32 0<br>
+; CHECK-NEXT: [[TMP14:%.*]] = bitcast i32* [[TMP13]] to <2 x i32>*<br>
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, <2 x i32>* [[TMP14]], align 4, !alias.scope !8, !noalias !11<br>
+; CHECK-NEXT: [[TMP15:%.*]] = add <2 x i32> [[WIDE_LOAD]], <i32 10, i32 10><br>
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[TMP11]]<br>
+; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, i32* [[TMP16]], i32 0<br>
+; CHECK-NEXT: [[TMP18:%.*]] = bitcast i32* [[TMP17]] to <2 x i32>*<br>
+; CHECK-NEXT: store <2 x i32> [[TMP15]], <2 x i32>* [[TMP18]], align 4, !alias.scope !11<br>
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2<br>
-; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]<br>
-; CHECK-NEXT: br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]<br>
+; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]<br>
+; CHECK-NEXT: br i1 [[TMP19]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]<br>
; CHECK: middle.block:<br>
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]<br>
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]<br>
@@ -277,31 +275,30 @@ define void @clamped_index_equal_dependence(i32* %A, i32* %B, i32 %N) {<br>
; CHECK: vector.scevcheck:<br>
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1<br>
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i2<br>
-; CHECK-NEXT: [[TMP2:%.*]] = add i2 [[TMP1]], 0<br>
-; CHECK-NEXT: [[TMP3:%.*]] = sub i2 0, [[TMP1]]<br>
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt i2 [[TMP3]], 0<br>
-; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i2 [[TMP2]], 0<br>
-; CHECK-NEXT: [[TMP6:%.*]] = icmp ugt i32 [[TMP0]], 3<br>
-; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]<br>
-; CHECK-NEXT: br i1 [[TMP7]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]<br>
+; CHECK-NEXT: [[TMP2:%.*]] = sub i2 0, [[TMP1]]<br>
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i2 [[TMP2]], 0<br>
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i2 [[TMP1]], 0<br>
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ugt i32 [[TMP0]], 3<br>
+; CHECK-NEXT: [[TMP6:%.*]] = or i1 [[TMP4]], [[TMP5]]<br>
+; CHECK-NEXT: br i1 [[TMP6]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]<br>
; CHECK: <a href="http://vector.ph" rel="noreferrer" target="_blank">vector.ph</a>:<br>
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 2<br>
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]<br>
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]<br>
; CHECK: vector.body:<br>
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]<br>
-; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[INDEX]], 0<br>
-; CHECK-NEXT: [[TMP9:%.*]] = urem i32 [[TMP8]], 4<br>
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i32 [[TMP9]]<br>
-; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, i32* [[TMP10]], i32 0<br>
-; CHECK-NEXT: [[TMP12:%.*]] = bitcast i32* [[TMP11]] to <2 x i32>*<br>
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, <2 x i32>* [[TMP12]], align 4<br>
-; CHECK-NEXT: [[TMP13:%.*]] = add <2 x i32> [[WIDE_LOAD]], <i32 10, i32 10><br>
-; CHECK-NEXT: [[TMP14:%.*]] = bitcast i32* [[TMP11]] to <2 x i32>*<br>
-; CHECK-NEXT: store <2 x i32> [[TMP13]], <2 x i32>* [[TMP14]], align 4<br>
+; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[INDEX]], 0<br>
+; CHECK-NEXT: [[TMP8:%.*]] = urem i32 [[TMP7]], 4<br>
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i32 [[TMP8]]<br>
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i32 0<br>
+; CHECK-NEXT: [[TMP11:%.*]] = bitcast i32* [[TMP10]] to <2 x i32>*<br>
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, <2 x i32>* [[TMP11]], align 4<br>
+; CHECK-NEXT: [[TMP12:%.*]] = add <2 x i32> [[WIDE_LOAD]], <i32 10, i32 10><br>
+; CHECK-NEXT: [[TMP13:%.*]] = bitcast i32* [[TMP10]] to <2 x i32>*<br>
+; CHECK-NEXT: store <2 x i32> [[TMP12]], <2 x i32>* [[TMP13]], align 4<br>
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2<br>
-; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]<br>
-; CHECK-NEXT: br i1 [[TMP15]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]<br>
+; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]<br>
+; CHECK-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]<br>
; CHECK: middle.block:<br>
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]<br>
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]<br>
<br>
diff --git a/llvm/test/Transforms/LoopVectorize/select-cmp-predicated.ll b/llvm/test/Transforms/LoopVectorize/select-cmp-predicated.ll<br>
index 4e64e94459a1d..7afa1b32f4e43 100644<br>
--- a/llvm/test/Transforms/LoopVectorize/select-cmp-predicated.ll<br>
+++ b/llvm/test/Transforms/LoopVectorize/select-cmp-predicated.ll<br>
@@ -56,8 +56,8 @@ define i32 @pred_select_const_i32_from_icmp(i32* noalias nocapture readonly %src<br>
;<br>
; CHECK-VF1IC2-LABEL: @pred_select_const_i32_from_icmp(<br>
; CHECK-VF1IC2: vector.body:<br>
-; CHECK-VF1IC2: [[VEC_PHI:%.*]] = phi i32 [ 0, %<a href="http://vector.ph" rel="noreferrer" target="_blank">vector.ph</a> ], [ [[PREDPHI:%.*]], %pred.load.continue4 ]<br>
-; CHECK-VF1IC2-NEXT: [[VEC_PHI2:%.*]] = phi i32 [ 0, %<a href="http://vector.ph" rel="noreferrer" target="_blank">vector.ph</a> ], [ [[PREDPHI5:%.*]], %pred.load.continue4 ]<br>
+; CHECK-VF1IC2: [[VEC_PHI:%.*]] = phi i32 [ 0, %<a href="http://vector.ph" rel="noreferrer" target="_blank">vector.ph</a> ], [ [[PREDPHI:%.*]], %pred.load.continue3 ]<br>
+; CHECK-VF1IC2-NEXT: [[VEC_PHI2:%.*]] = phi i32 [ 0, %<a href="http://vector.ph" rel="noreferrer" target="_blank">vector.ph</a> ], [ [[PREDPHI5:%.*]], %pred.load.continue3 ]<br>
; CHECK-VF1IC2: [[TMP0:%.*]] = getelementptr inbounds i32, i32* [[SRC1:%.*]], i64 {{%.*}}<br>
; CHECK-VF1IC2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[SRC1]], i64 {{%.*}}<br>
; CHECK-VF1IC2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP0]], align 4<br>
@@ -71,13 +71,13 @@ define i32 @pred_select_const_i32_from_icmp(i32* noalias nocapture readonly %src<br>
; CHECK-VF1IC2-NEXT: br label %pred.load.continue<br>
; CHECK-VF1IC2: pred.load.continue:<br>
; CHECK-VF1IC2-NEXT: [[TMP8:%.*]] = phi i32 [ poison, %vector.body ], [ [[TMP7]], %pred.load.if ]<br>
-; CHECK-VF1IC2-NEXT: br i1 [[TMP5]], label %pred.load.if3, label %pred.load.continue4<br>
-; CHECK-VF1IC2: pred.load.if3:<br>
+; CHECK-VF1IC2-NEXT: br i1 [[TMP5]], label %pred.load.if2, label %pred.load.continue3<br>
+; CHECK-VF1IC2: pred.load.if2:<br>
; CHECK-VF1IC2-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, i32* [[SRC2]], i64 {{%.*}}<br>
; CHECK-VF1IC2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4<br>
-; CHECK-VF1IC2-NEXT: br label %pred.load.continue4<br>
-; CHECK-VF1IC2: pred.load.continue4:<br>
-; CHECK-VF1IC2-NEXT: [[TMP11:%.*]] = phi i32 [ poison, %pred.load.continue ], [ [[TMP10]], %pred.load.if3 ]<br>
+; CHECK-VF1IC2-NEXT: br label %pred.load.continue3<br>
+; CHECK-VF1IC2: pred.load.continue3:<br>
+; CHECK-VF1IC2-NEXT: [[TMP11:%.*]] = phi i32 [ poison, %pred.load.continue ], [ [[TMP10]], %pred.load.if2 ]<br>
; CHECK-VF1IC2-NEXT: [[TMP12:%.*]] = icmp eq i32 [[TMP8]], 2<br>
; CHECK-VF1IC2-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP11]], 2<br>
; CHECK-VF1IC2-NEXT: [[TMP14:%.*]] = select i1 [[TMP12]], i32 1, i32 [[VEC_PHI]]<br>
<br>
diff --git a/llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll b/llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll<br>
index bb901ed70a827..59c1221cec241 100644<br>
--- a/llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll<br>
+++ b/llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll<br>
@@ -17,13 +17,12 @@ define void @VF1-VPlanExe() {<br>
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]<br>
; CHECK: vector.body:<br>
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]<br>
-; CHECK-NEXT: [[INDUCTION:%.*]] = add i64 [[INDEX]], 0<br>
-; CHECK-NEXT: [[INDUCTION1:%.*]] = add i64 [[INDEX]], 1<br>
-; CHECK-NEXT: [[INDUCTION2:%.*]] = add i64 [[INDEX]], 2<br>
-; CHECK-NEXT: [[INDUCTION3:%.*]] = add i64 [[INDEX]], 3<br>
+; CHECK-NEXT: [[INDUCTION:%.*]] = add i64 [[INDEX]], 1<br>
+; CHECK-NEXT: [[INDUCTION1:%.*]] = add i64 [[INDEX]], 2<br>
+; CHECK-NEXT: [[INDUCTION2:%.*]] = add i64 [[INDEX]], 3<br>
; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4<br>
; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16<br>
-; CHECK-NEXT: br i1 [[TMP0]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !0<br>
+; CHECK-NEXT: br i1 [[TMP0]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]<br>
; CHECK: middle.block:<br>
; CHECK-NEXT: br i1 true, label [[FOR_COND_CLEANUP:%.*]], label [[SCALAR_PH]]<br>
; CHECK: <a href="http://scalar.ph" rel="noreferrer" target="_blank">scalar.ph</a>:<br>
@@ -35,7 +34,7 @@ define void @VF1-VPlanExe() {<br>
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]<br>
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1<br>
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 15<br>
-; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop !2<br>
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]]<br>
;<br>
entry:<br>
br label %for.body<br>
@@ -60,17 +59,16 @@ define void @VF1-VPWidenCanonicalIVRecipeExe(double* %ptr1) {<br>
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]<br>
; CHECK: vector.body:<br>
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]<br>
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0<br>
-; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr double, double* [[PTR1]], i64 [[TMP0]]<br>
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1<br>
-; CHECK-NEXT: [[NEXT_GEP1:%.*]] = getelementptr double, double* [[PTR1]], i64 [[TMP1]]<br>
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2<br>
-; CHECK-NEXT: [[NEXT_GEP2:%.*]] = getelementptr double, double* [[PTR1]], i64 [[TMP2]]<br>
-; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3<br>
-; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr double, double* [[PTR1]], i64 [[TMP3]]<br>
+; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr double, double* [[PTR1]], i64 [[INDEX]]<br>
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 1<br>
+; CHECK-NEXT: [[NEXT_GEP1:%.*]] = getelementptr double, double* [[PTR1]], i64 [[TMP0]]<br>
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 2<br>
+; CHECK-NEXT: [[NEXT_GEP2:%.*]] = getelementptr double, double* [[PTR1]], i64 [[TMP1]]<br>
+; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 3<br>
+; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr double, double* [[PTR1]], i64 [[TMP2]]<br>
; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4<br>
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16<br>
-; CHECK-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !3<br>
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16<br>
+; CHECK-NEXT: br i1 [[TMP3]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]<br>
; CHECK: middle.block:<br>
; CHECK-NEXT: br i1 true, label [[FOR_COND_CLEANUP:%.*]], label [[SCALAR_PH]]<br>
; CHECK: <a href="http://scalar.ph" rel="noreferrer" target="_blank">scalar.ph</a>:<br>
@@ -82,7 +80,7 @@ define void @VF1-VPWidenCanonicalIVRecipeExe(double* %ptr1) {<br>
; CHECK-NEXT: [[ADDR:%.*]] = phi double* [ [[PTR:%.*]], [[FOR_BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]<br>
; CHECK-NEXT: [[PTR]] = getelementptr inbounds double, double* [[ADDR]], i64 1<br>
; CHECK-NEXT: [[COND:%.*]] = icmp eq double* [[PTR]], [[PTR2]]<br>
-; CHECK-NEXT: br i1 [[COND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop !4<br>
+; CHECK-NEXT: br i1 [[COND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]<br>
;<br>
entry:<br>
%ptr2 = getelementptr inbounds double, double* %ptr1, i64 15<br>
<br>
diff --git a/llvm/test/Transforms/LoopVectorize/unroll_nonlatch.ll b/llvm/test/Transforms/LoopVectorize/unroll_nonlatch.ll<br>
index e2d25cc42f56d..c4d95880736db 100644<br>
--- a/llvm/test/Transforms/LoopVectorize/unroll_nonlatch.ll<br>
+++ b/llvm/test/Transforms/LoopVectorize/unroll_nonlatch.ll<br>
@@ -16,10 +16,9 @@ define void @test(double* %data) {<br>
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]<br>
; CHECK: vector.body:<br>
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]<br>
-; CHECK-NEXT: [[INDUCTION:%.*]] = add i64 [[INDEX]], 0<br>
-; CHECK-NEXT: [[INDUCTION1:%.*]] = add i64 [[INDEX]], 1<br>
-; CHECK-NEXT: [[TMP0:%.*]] = shl nuw nsw i64 [[INDUCTION]], 1<br>
-; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i64 [[INDUCTION1]], 1<br>
+; CHECK-NEXT: [[INDUCTION:%.*]] = add i64 [[INDEX]], 1<br>
+; CHECK-NEXT: [[TMP0:%.*]] = shl nuw nsw i64 [[INDEX]], 1<br>
+; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i64 [[INDUCTION]], 1<br>
; CHECK-NEXT: [[TMP2:%.*]] = or i64 [[TMP0]], 1<br>
; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], 1<br>
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds double, double* [[DATA:%.*]], i64 [[TMP2]]<br>
<br>
diff --git a/llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll b/llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll<br>
index 0e02297fdde1a..74890576146ac 100644<br>
--- a/llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll<br>
+++ b/llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll<br>
@@ -28,18 +28,17 @@ define void @basic_loop(i8* nocapture readonly %ptr, i32 %size, i8** %pos) {<br>
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]<br>
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i32 [[SIZE]], [[INDEX]]<br>
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[OFFSET_IDX]], 0<br>
-; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 0<br>
-; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, i8* [[PTR]], i32 [[TMP1]]<br>
-; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8* [[NEXT_GEP]], i32 1<br>
-; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i32 0<br>
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8* [[TMP3]] to <4 x i8>*<br>
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, <4 x i8>* [[TMP4]], align 1<br>
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, i8* [[NEXT_GEP]], i32 0<br>
-; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to <4 x i8>*<br>
-; CHECK-NEXT: store <4 x i8> [[WIDE_LOAD]], <4 x i8>* [[TMP6]], align 1<br>
+; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, i8* [[PTR]], i32 [[INDEX]]<br>
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, i8* [[NEXT_GEP]], i32 1<br>
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8* [[TMP1]], i32 0<br>
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to <4 x i8>*<br>
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, <4 x i8>* [[TMP3]], align 1<br>
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[NEXT_GEP]], i32 0<br>
+; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to <4 x i8>*<br>
+; CHECK-NEXT: store <4 x i8> [[WIDE_LOAD]], <4 x i8>* [[TMP5]], align 1<br>
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4<br>
-; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]<br>
-; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !0<br>
+; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]<br>
+; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]<br>
; CHECK: middle.block:<br>
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[SIZE]], [[N_VEC]]<br>
; CHECK-NEXT: br i1 [[CMP_N]], label [[END:%.*]], label [[SCALAR_PH]]<br>
@@ -52,10 +51,10 @@ define void @basic_loop(i8* nocapture readonly %ptr, i32 %size, i8** %pos) {<br>
; CHECK-NEXT: [[BUFF:%.*]] = phi i8* [ [[INCDEC_PTR:%.*]], [[BODY]] ], [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ]<br>
; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i8, i8* [[BUFF]], i32 1<br>
; CHECK-NEXT: [[DEC]] = add nsw i32 [[DEC66]], -1<br>
-; CHECK-NEXT: [[TMP8:%.*]] = load i8, i8* [[INCDEC_PTR]], align 1<br>
-; CHECK-NEXT: store i8 [[TMP8]], i8* [[BUFF]], align 1<br>
+; CHECK-NEXT: [[TMP7:%.*]] = load i8, i8* [[INCDEC_PTR]], align 1<br>
+; CHECK-NEXT: store i8 [[TMP7]], i8* [[BUFF]], align 1<br>
; CHECK-NEXT: [[TOBOOL11:%.*]] = icmp eq i32 [[DEC]], 0<br>
-; CHECK-NEXT: br i1 [[TOBOOL11]], label [[END]], label [[BODY]], !llvm.loop !2<br>
+; CHECK-NEXT: br i1 [[TOBOOL11]], label [[END]], label [[BODY]], !llvm.loop [[LOOP2:![0-9]+]]<br>
; CHECK: end:<br>
; CHECK-NEXT: [[INCDEC_PTR_LCSSA:%.*]] = phi i8* [ [[INCDEC_PTR]], [[BODY]] ], [ [[IND_END2]], [[MIDDLE_BLOCK]] ]<br>
; CHECK-NEXT: store i8* [[INCDEC_PTR_LCSSA]], i8** [[POS]], align 4<br>
@@ -96,18 +95,17 @@ define void @metadata(i8* nocapture readonly %ptr, i32 %size, i8** %pos) {<br>
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]<br>
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i32 [[SIZE]], [[INDEX]]<br>
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[OFFSET_IDX]], 0<br>
-; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 0<br>
-; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, i8* [[PTR]], i32 [[TMP1]]<br>
-; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8* [[NEXT_GEP]], i32 1<br>
-; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i32 0<br>
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8* [[TMP3]] to <4 x i8>*<br>
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, <4 x i8>* [[TMP4]], align 1<br>
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, i8* [[NEXT_GEP]], i32 0<br>
-; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to <4 x i8>*<br>
-; CHECK-NEXT: store <4 x i8> [[WIDE_LOAD]], <4 x i8>* [[TMP6]], align 1<br>
+; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, i8* [[PTR]], i32 [[INDEX]]<br>
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, i8* [[NEXT_GEP]], i32 1<br>
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8* [[TMP1]], i32 0<br>
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to <4 x i8>*<br>
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, <4 x i8>* [[TMP3]], align 1<br>
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[NEXT_GEP]], i32 0<br>
+; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to <4 x i8>*<br>
+; CHECK-NEXT: store <4 x i8> [[WIDE_LOAD]], <4 x i8>* [[TMP5]], align 1<br>
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4<br>
-; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]<br>
-; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !4<br>
+; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]<br>
+; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]<br>
; CHECK: middle.block:<br>
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[SIZE]], [[N_VEC]]<br>
; CHECK-NEXT: br i1 [[CMP_N]], label [[END:%.*]], label [[SCALAR_PH]]<br>
@@ -120,10 +118,10 @@ define void @metadata(i8* nocapture readonly %ptr, i32 %size, i8** %pos) {<br>
; CHECK-NEXT: [[BUFF:%.*]] = phi i8* [ [[INCDEC_PTR:%.*]], [[BODY]] ], [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ]<br>
; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i8, i8* [[BUFF]], i32 1<br>
; CHECK-NEXT: [[DEC]] = add nsw i32 [[DEC66]], -1<br>
-; CHECK-NEXT: [[TMP8:%.*]] = load i8, i8* [[INCDEC_PTR]], align 1<br>
-; CHECK-NEXT: store i8 [[TMP8]], i8* [[BUFF]], align 1<br>
+; CHECK-NEXT: [[TMP7:%.*]] = load i8, i8* [[INCDEC_PTR]], align 1<br>
+; CHECK-NEXT: store i8 [[TMP7]], i8* [[BUFF]], align 1<br>
; CHECK-NEXT: [[TOBOOL11:%.*]] = icmp eq i32 [[DEC]], 0<br>
-; CHECK-NEXT: br i1 [[TOBOOL11]], label [[END]], label [[BODY]], !llvm.loop !5<br>
+; CHECK-NEXT: br i1 [[TOBOOL11]], label [[END]], label [[BODY]], !llvm.loop [[LOOP5:![0-9]+]]<br>
; CHECK: end:<br>
; CHECK-NEXT: [[INCDEC_PTR_LCSSA:%.*]] = phi i8* [ [[INCDEC_PTR]], [[BODY]] ], [ [[IND_END2]], [[MIDDLE_BLOCK]] ]<br>
; CHECK-NEXT: store i8* [[INCDEC_PTR_LCSSA]], i8** [[POS]], align 4<br>
<br>
diff --git a/llvm/test/Transforms/LoopVersioning/wrapping-pointer-versioning.ll b/llvm/test/Transforms/LoopVersioning/wrapping-pointer-versioning.ll<br>
index 17862145f466a..f6135d627c09f 100644<br>
--- a/llvm/test/Transforms/LoopVersioning/wrapping-pointer-versioning.ll<br>
+++ b/llvm/test/Transforms/LoopVersioning/wrapping-pointer-versioning.ll<br>
@@ -34,24 +34,23 @@ define void @f1(i16* noalias %a,<br>
; LV-NEXT: [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP1]])<br>
; LV-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0<br>
; LV-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1<br>
-; LV-NEXT: [[TMP2:%.*]] = add i32 [[MUL_RESULT]], 0<br>
-; LV-NEXT: [[TMP3:%.*]] = sub i32 0, [[MUL_RESULT]]<br>
-; LV-NEXT: [[TMP4:%.*]] = icmp ugt i32 [[TMP3]], 0<br>
-; LV-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP2]], 0<br>
-; LV-NEXT: [[TMP6:%.*]] = icmp ugt i64 [[TMP0]], 4294967295<br>
-; LV-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]<br>
-; LV-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW]]<br>
+; LV-NEXT: [[TMP2:%.*]] = sub i32 0, [[MUL_RESULT]]<br>
+; LV-NEXT: [[TMP3:%.*]] = icmp ugt i32 [[TMP2]], 0<br>
+; LV-NEXT: [[TMP4:%.*]] = icmp ult i32 [[MUL_RESULT]], 0<br>
+; LV-NEXT: [[TMP5:%.*]] = icmp ugt i64 [[TMP0]], 4294967295<br>
+; LV-NEXT: [[TMP6:%.*]] = or i1 [[TMP4]], [[TMP5]]<br>
+; LV-NEXT: [[TMP7:%.*]] = or i1 [[TMP6]], [[MUL_OVERFLOW]]<br>
; LV-NEXT: [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[TMP0]])<br>
; LV-NEXT: [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0<br>
; LV-NEXT: [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1<br>
-; LV-NEXT: [[TMP9:%.*]] = sub i64 0, [[MUL_RESULT3]]<br>
-; LV-NEXT: [[TMP10:%.*]] = getelementptr i8, i8* [[A5]], i64 [[MUL_RESULT3]]<br>
-; LV-NEXT: [[TMP11:%.*]] = getelementptr i8, i8* [[A5]], i64 [[TMP9]]<br>
-; LV-NEXT: [[TMP12:%.*]] = icmp ugt i8* [[TMP11]], [[A5]]<br>
-; LV-NEXT: [[TMP13:%.*]] = icmp ult i8* [[TMP10]], [[A5]]<br>
-; LV-NEXT: [[TMP14:%.*]] = or i1 [[TMP13]], [[MUL_OVERFLOW4]]<br>
-; LV-NEXT: [[TMP15:%.*]] = or i1 [[TMP8]], [[TMP14]]<br>
-; LV-NEXT: br i1 [[TMP15]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH:%.*]]<br>
+; LV-NEXT: [[TMP8:%.*]] = sub i64 0, [[MUL_RESULT3]]<br>
+; LV-NEXT: [[TMP9:%.*]] = getelementptr i8, i8* [[A5]], i64 [[MUL_RESULT3]]<br>
+; LV-NEXT: [[TMP10:%.*]] = getelementptr i8, i8* [[A5]], i64 [[TMP8]]<br>
+; LV-NEXT: [[TMP11:%.*]] = icmp ugt i8* [[TMP10]], [[A5]]<br>
+; LV-NEXT: [[TMP12:%.*]] = icmp ult i8* [[TMP9]], [[A5]]<br>
+; LV-NEXT: [[TMP13:%.*]] = or i1 [[TMP12]], [[MUL_OVERFLOW4]]<br>
+; LV-NEXT: [[TMP14:%.*]] = or i1 [[TMP7]], [[TMP13]]<br>
+; LV-NEXT: br i1 [[TMP14]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH:%.*]]<br>
; LV: for.body.ph.lver.orig:<br>
; LV-NEXT: br label [[FOR_BODY_LVER_ORIG:%.*]]<br>
; LV: for.body.lver.orig:<br>
@@ -271,24 +270,23 @@ define void @f3(i16* noalias %a,<br>
; LV-NEXT: [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP1]])<br>
; LV-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0<br>
; LV-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1<br>
-; LV-NEXT: [[TMP2:%.*]] = add i32 [[MUL_RESULT]], 0<br>
-; LV-NEXT: [[TMP3:%.*]] = sub i32 0, [[MUL_RESULT]]<br>
-; LV-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[TMP3]], 0<br>
-; LV-NEXT: [[TMP5:%.*]] = icmp slt i32 [[TMP2]], 0<br>
-; LV-NEXT: [[TMP6:%.*]] = icmp ugt i64 [[TMP0]], 4294967295<br>
-; LV-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]<br>
-; LV-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW]]<br>
+; LV-NEXT: [[TMP2:%.*]] = sub i32 0, [[MUL_RESULT]]<br>
+; LV-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[TMP2]], 0<br>
+; LV-NEXT: [[TMP4:%.*]] = icmp slt i32 [[MUL_RESULT]], 0<br>
+; LV-NEXT: [[TMP5:%.*]] = icmp ugt i64 [[TMP0]], 4294967295<br>
+; LV-NEXT: [[TMP6:%.*]] = or i1 [[TMP4]], [[TMP5]]<br>
+; LV-NEXT: [[TMP7:%.*]] = or i1 [[TMP6]], [[MUL_OVERFLOW]]<br>
; LV-NEXT: [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[TMP0]])<br>
; LV-NEXT: [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0<br>
; LV-NEXT: [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1<br>
-; LV-NEXT: [[TMP9:%.*]] = sub i64 0, [[MUL_RESULT3]]<br>
-; LV-NEXT: [[TMP10:%.*]] = getelementptr i8, i8* [[A5]], i64 [[MUL_RESULT3]]<br>
-; LV-NEXT: [[TMP11:%.*]] = getelementptr i8, i8* [[A5]], i64 [[TMP9]]<br>
-; LV-NEXT: [[TMP12:%.*]] = icmp ugt i8* [[TMP11]], [[A5]]<br>
-; LV-NEXT: [[TMP13:%.*]] = icmp ult i8* [[TMP10]], [[A5]]<br>
-; LV-NEXT: [[TMP14:%.*]] = or i1 [[TMP13]], [[MUL_OVERFLOW4]]<br>
-; LV-NEXT: [[TMP15:%.*]] = or i1 [[TMP8]], [[TMP14]]<br>
-; LV-NEXT: br i1 [[TMP15]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH:%.*]]<br>
+; LV-NEXT: [[TMP8:%.*]] = sub i64 0, [[MUL_RESULT3]]<br>
+; LV-NEXT: [[TMP9:%.*]] = getelementptr i8, i8* [[A5]], i64 [[MUL_RESULT3]]<br>
+; LV-NEXT: [[TMP10:%.*]] = getelementptr i8, i8* [[A5]], i64 [[TMP8]]<br>
+; LV-NEXT: [[TMP11:%.*]] = icmp ugt i8* [[TMP10]], [[A5]]<br>
+; LV-NEXT: [[TMP12:%.*]] = icmp ult i8* [[TMP9]], [[A5]]<br>
+; LV-NEXT: [[TMP13:%.*]] = or i1 [[TMP12]], [[MUL_OVERFLOW4]]<br>
+; LV-NEXT: [[TMP14:%.*]] = or i1 [[TMP7]], [[TMP13]]<br>
+; LV-NEXT: br i1 [[TMP14]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH:%.*]]<br>
; LV: for.body.ph.lver.orig:<br>
; LV-NEXT: br label [[FOR_BODY_LVER_ORIG:%.*]]<br>
; LV: for.body.lver.orig:<br>
<br>
diff --git a/llvm/unittests/IR/PatternMatch.cpp b/llvm/unittests/IR/PatternMatch.cpp<br>
index 598dcdff943f8..7023e5a41fe7b 100644<br>
--- a/llvm/unittests/IR/PatternMatch.cpp<br>
+++ b/llvm/unittests/IR/PatternMatch.cpp<br>
@@ -479,19 +479,19 @@ TEST_F(PatternMatchTest, SpecificIntSLE) {<br>
}<br>
<br>
TEST_F(PatternMatchTest, Unless) {<br>
- Value *X = IRB.CreateAdd(IRB.getInt32(1), IRB.getInt32(0));<br>
+ Value *X = IRB.CreateAdd(IRB.getInt32(1), IRB.getInt32(-1));<br>
<br>
- EXPECT_TRUE(m_Add(m_One(), m_Zero()).match(X));<br>
- EXPECT_FALSE(m_Add(m_Zero(), m_One()).match(X));<br>
+ EXPECT_TRUE(m_Add(m_One(), m_AllOnes()).match(X));<br>
+ EXPECT_FALSE(m_Add(m_AllOnes(), m_One()).match(X));<br>
<br>
- EXPECT_FALSE(m_Unless(m_Add(m_One(), m_Zero())).match(X));<br>
- EXPECT_TRUE(m_Unless(m_Add(m_Zero(), m_One())).match(X));<br>
+ EXPECT_FALSE(m_Unless(m_Add(m_One(), m_AllOnes())).match(X));<br>
+ EXPECT_TRUE(m_Unless(m_Add(m_AllOnes(), m_One())).match(X));<br>
<br>
- EXPECT_TRUE(m_c_Add(m_One(), m_Zero()).match(X));<br>
- EXPECT_TRUE(m_c_Add(m_Zero(), m_One()).match(X));<br>
+ EXPECT_TRUE(m_c_Add(m_One(), m_AllOnes()).match(X));<br>
+ EXPECT_TRUE(m_c_Add(m_AllOnes(), m_One()).match(X));<br>
<br>
- EXPECT_FALSE(m_Unless(m_c_Add(m_One(), m_Zero())).match(X));<br>
- EXPECT_FALSE(m_Unless(m_c_Add(m_Zero(), m_One())).match(X));<br>
+ EXPECT_FALSE(m_Unless(m_c_Add(m_One(), m_AllOnes())).match(X));<br>
+ EXPECT_FALSE(m_Unless(m_c_Add(m_AllOnes(), m_One())).match(X));<br>
}<br>
<br>
TEST_F(PatternMatchTest, ZExtSExtSelf) {<br>
<br>
<br>
<br>
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</blockquote></div>