<div dir="ltr">Was seeing some test failures when built with shared libraries as well - different numbers of cycles:<div><br></div><div># CHECK-NEXT: Total Cycles: 94<br> ^<br><stdin>:2:17: note: scanning from here<br>Instructions: 36<br> ^<br><stdin>:3:1: note: possible intended match here<br>Total Cycles: 91<br>^<br></div><div><br></div><div>-eric</div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Wed, Jul 7, 2021 at 11:50 PM Patrick Holland via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
Author: Patrick Holland<br>
Date: 2021-07-07T20:48:42-07:00<br>
New Revision: d38b9f1f31b1fa8ee885cfcd4ee7bd69771088c8<br>
<br>
URL: <a href="https://github.com/llvm/llvm-project/commit/d38b9f1f31b1fa8ee885cfcd4ee7bd69771088c8" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/d38b9f1f31b1fa8ee885cfcd4ee7bd69771088c8</a><br>
DIFF: <a href="https://github.com/llvm/llvm-project/commit/d38b9f1f31b1fa8ee885cfcd4ee7bd69771088c8.diff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/d38b9f1f31b1fa8ee885cfcd4ee7bd69771088c8.diff</a><br>
<br>
LOG: Revert "[MCA] [AMDGPU] Adding an implementation to AMDGPUCustomBehaviour for handling s_waitcnt instructions."<br>
<br>
Build failures when building with shared libraries. Reverting until I can fix.<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D104730" rel="noreferrer" target="_blank">https://reviews.llvm.org/D104730</a><br>
<br>
Added: <br>
<br>
<br>
Modified: <br>
llvm/lib/Target/AMDGPU/SISchedule.td<br>
llvm/test/tools/llvm-mca/AMDGPU/gfx10-double.s<br>
llvm/tools/llvm-mca/lib/AMDGPU/AMDGPUCustomBehaviour.cpp<br>
llvm/tools/llvm-mca/lib/AMDGPU/AMDGPUCustomBehaviour.h<br>
<br>
Removed: <br>
llvm/test/tools/llvm-mca/AMDGPU/gfx9-retireooo.s<br>
<br>
<br>
################################################################################<br>
diff --git a/llvm/lib/Target/AMDGPU/SISchedule.td b/llvm/lib/Target/AMDGPU/SISchedule.td<br>
index 0792b303b830..b24c061af7ab 100644<br>
--- a/llvm/lib/Target/AMDGPU/SISchedule.td<br>
+++ b/llvm/lib/Target/AMDGPU/SISchedule.td<br>
@@ -137,7 +137,6 @@ def MIReadVGPR : SchedReadVariant<[<br>
// The latency values are 1 / (operations / cycle) / 4.<br>
multiclass SICommonWriteRes {<br>
<br>
- let RetireOOO = 1 in { // llvm-mca specific flag<br>
def : HWWriteRes<WriteBranch, [HWBranch], 8>;<br>
def : HWWriteRes<WriteExport, [HWExport], 4>;<br>
def : HWWriteRes<WriteLDS, [HWLGKM], 5>; // Can be between 2 and 64<br>
@@ -160,7 +159,6 @@ multiclass SICommonWriteRes {<br>
def : HWWriteRes<Write8PassMAI, [HWXDL], 8>;<br>
let ResourceCycles = [16] in<br>
def : HWWriteRes<Write16PassMAI, [HWXDL], 16>;<br>
- } // End RetireOOO = 1<br>
<br>
def : ReadAdvance<MIVGPRRead, -2>;<br>
<br>
@@ -184,7 +182,6 @@ let SchedModel = SIFullSpeedModel in {<br>
<br>
defm : SICommonWriteRes;<br>
<br>
-let RetireOOO = 1 in { // llvm-mca specific flag<br>
def : HWVALUWriteRes<Write64Bit, 2>;<br>
def : HWVALUWriteRes<WriteIntMul, 4>;<br>
def : HWVALUWriteRes<WriteFloatFMA, 1>;<br>
@@ -192,7 +189,6 @@ def : HWVALUWriteRes<WriteDouble, 4>;<br>
def : HWVALUWriteRes<WriteDoubleAdd, 2>;<br>
def : HWVALUWriteRes<WriteDoubleCvt, 4>;<br>
def : HWVALUWriteRes<WriteTrans64, 4>;<br>
-} // End RetireOOO = 1<br>
<br>
def : InstRW<[WriteCopy], (instrs COPY)>;<br>
<br>
@@ -202,7 +198,6 @@ let SchedModel = SIQuarterSpeedModel in {<br>
<br>
defm : SICommonWriteRes;<br>
<br>
-let RetireOOO = 1 in { // llvm-mca specific flag<br>
def : HWVALUWriteRes<Write64Bit, 2>;<br>
def : HWVALUWriteRes<WriteIntMul, 4>;<br>
def : HWVALUWriteRes<WriteFloatFMA, 16>;<br>
@@ -210,7 +205,6 @@ def : HWVALUWriteRes<WriteDouble, 16>;<br>
def : HWVALUWriteRes<WriteDoubleAdd, 8>;<br>
def : HWVALUWriteRes<WriteDoubleCvt, 4>;<br>
def : HWVALUWriteRes<WriteTrans64, 16>;<br>
-} // End RetireOOO = 1<br>
<br>
def : InstRW<[WriteCopy], (instrs COPY)>;<br>
def : InstRW<[Write64Bit, MIReadVGPR], (instregex "^V_ACCVGPR_WRITE_B32_e64$")>;<br>
@@ -224,7 +218,6 @@ let SchedModel = SIDPFullSpeedModel in {<br>
<br>
defm : SICommonWriteRes;<br>
<br>
-let RetireOOO = 1 in { // llvm-mca specific flag<br>
def : HWVALUWriteRes<WriteFloatFMA, 1>;<br>
def : HWVALUWriteRes<WriteDouble, 1>;<br>
def : HWVALUWriteRes<WriteDoubleAdd, 1>;<br>
@@ -232,7 +225,6 @@ def : HWVALUWriteRes<WriteDoubleCvt, 1>;<br>
def : HWVALUWriteRes<WriteTrans64, 4>;<br>
def : HWVALUWriteRes<WriteIntMul, 1>;<br>
def : HWVALUWriteRes<Write64Bit, 1>;<br>
-} // End RetireOOO = 1<br>
<br>
def : InstRW<[WriteCopy], (instrs COPY)>;<br>
def : InstRW<[Write64Bit], (instregex "^V_ACCVGPR_WRITE_B32_e64$")>;<br>
@@ -248,7 +240,6 @@ let SchedModel = GFX10SpeedModel in {<br>
<br>
// The latency values are 1 / (operations / cycle).<br>
// Add 1 stall cycle for VGPR read.<br>
-let RetireOOO = 1 in { // llvm-mca specific flag<br>
def : HWWriteRes<Write32Bit, [HWVALU, HWRC], 5>;<br>
def : HWWriteRes<WriteFloatCvt, [HWVALU, HWRC], 5>;<br>
def : HWWriteRes<Write64Bit, [HWVALU, HWRC], 6>;<br>
@@ -268,7 +259,6 @@ def : HWWriteRes<WriteSALU, [HWSALU, HWRC], 2>;<br>
def : HWWriteRes<WriteSMEM, [HWLGKM, HWRC], 20>;<br>
def : HWWriteRes<WriteVMEM, [HWVMEM, HWRC], 320>;<br>
def : HWWriteRes<WriteBarrier, [HWBranch], 2000>;<br>
-} // End RetireOOO = 1<br>
<br>
def : InstRW<[WriteCopy], (instrs COPY)>;<br>
<br>
<br>
diff --git a/llvm/test/tools/llvm-mca/AMDGPU/gfx10-double.s b/llvm/test/tools/llvm-mca/AMDGPU/gfx10-double.s<br>
index 00b429ef6d67..0ffdad05cfa6 100644<br>
--- a/llvm/test/tools/llvm-mca/AMDGPU/gfx10-double.s<br>
+++ b/llvm/test/tools/llvm-mca/AMDGPU/gfx10-double.s<br>
@@ -41,12 +41,12 @@ v_sqrt_f64 v[4:5], v[4:5]<br>
<br>
# CHECK: Iterations: 1<br>
# CHECK-NEXT: Instructions: 28<br>
-# CHECK-NEXT: Total Cycles: 205<br>
+# CHECK-NEXT: Total Cycles: 224<br>
# CHECK-NEXT: Total uOps: 29<br>
<br>
# CHECK: Dispatch Width: 1<br>
-# CHECK-NEXT: uOps Per Cycle: 0.14<br>
-# CHECK-NEXT: IPC: 0.14<br>
+# CHECK-NEXT: uOps Per Cycle: 0.13<br>
+# CHECK-NEXT: IPC: 0.13<br>
# CHECK-NEXT: Block RThroughput: 29.0<br>
<br>
# CHECK: Instruction Info:<br>
@@ -133,37 +133,37 @@ v_sqrt_f64 v[4:5], v[4:5]<br>
# CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_sqrt_f64_e32 v[4:5], v[4:5]<br>
<br>
# CHECK: Timeline view:<br>
-# CHECK-NEXT: 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789<br>
-# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 01234<br>
-<br>
-# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_cvt_i32_f64_e32 v0, v[0:1]<br>
-# CHECK-NEXT: [0,1] .DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_cvt_f64_i32_e32 v[2:3], v2<br>
-# CHECK-NEXT: [0,2] . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_cvt_f32_f64_e32 v4, v[4:5]<br>
-# CHECK-NEXT: [0,3] . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_cvt_f64_f32_e32 v[6:7], v6<br>
-# CHECK-NEXT: [0,4] . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_cvt_u32_f64_e32 v8, v[8:9]<br>
-# CHECK-NEXT: [0,5] . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_cvt_f64_u32_e32 v[10:11], v10<br>
-# CHECK-NEXT: [0,6] . . . . . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_frexp_exp_i32_f64_e32 v0, v[0:1]<br>
-# CHECK-NEXT: [0,7] . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_frexp_mant_f64_e32 v[2:3], v[2:3]<br>
-# CHECK-NEXT: [0,8] . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_fract_f64_e32 v[4:5], v[4:5]<br>
-# CHECK-NEXT: [0,9] . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_trunc_f64_e32 v[0:1], v[0:1]<br>
-# CHECK-NEXT: [0,10] . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_ceil_f64_e32 v[2:3], v[2:3]<br>
-# CHECK-NEXT: [0,11] . . . . . . . . . .DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_rndne_f64_e32 v[4:5], v[4:5]<br>
-# CHECK-NEXT: [0,12] . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . . . . . . . . . . . . . . . . . . . . . . . v_floor_f64_e32 v[6:7], v[6:7]<br>
-# CHECK-NEXT: [0,13] . . . . . . . . . . . . . .DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . v_fma_f64 v[0:1], v[0:1], v[0:1], v[0:1]<br>
-# CHECK-NEXT: [0,14] . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . . . . . . . . . . . . . . . . . . . v_add_f64 v[2:3], v[2:3], v[2:3]<br>
-# CHECK-NEXT: [0,15] . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . v_mul_f64 v[4:5], v[4:5], v[4:5]<br>
-# CHECK-NEXT: [0,16] . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . v_min_f64 v[6:7], v[6:7], v[6:7]<br>
-# CHECK-NEXT: [0,17] . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . v_max_f64 v[8:9], v[8:9], v[8:9]<br>
-# CHECK-NEXT: [0,18] . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . v_div_fmas_f64 v[0:1], v[0:1], v[0:1], v[0:1]<br>
-# CHECK-NEXT: [0,19] . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . v_div_fixup_f64 v[0:1], v[0:1], v[0:1], v[0:1]<br>
-# CHECK-NEXT: [0,20] . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . . . . . . v_ldexp_f64 v[2:3], v[2:3], v0<br>
-# CHECK-NEXT: [0,21] . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . v_div_scale_f64 v[0:1], vcc_lo, v[0:1], v[0:1], v[0:1]<br>
-# CHECK-NEXT: [0,22] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . v_trig_preop_f64 v[2:3], v[2:3], v0<br>
-# CHECK-NEXT: [0,23] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DeeeeeeeeeeeeeeeeeeeeeE . . . . . . v_cmp_eq_f64_e32 vcc_lo, v[0:1], v[0:1]<br>
-# CHECK-NEXT: [0,24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE. . v_cmp_class_f64_e64 vcc_lo, v[2:3], s0<br>
-# CHECK-NEXT: [0,25] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeE . v_rcp_f64_e32 v[0:1], v[0:1]<br>
-# CHECK-NEXT: [0,26] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeE. v_rsq_f64_e32 v[2:3], v[2:3]<br>
-# CHECK-NEXT: [0,27] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeE v_sqrt_f64_e32 v[4:5], v[4:5]<br>
+# CHECK-NEXT: 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789<br>
+# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123<br>
+<br>
+# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_cvt_i32_f64_e32 v0, v[0:1]<br>
+# CHECK-NEXT: [0,1] .DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_cvt_f64_i32_e32 v[2:3], v2<br>
+# CHECK-NEXT: [0,2] . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_cvt_f32_f64_e32 v4, v[4:5]<br>
+# CHECK-NEXT: [0,3] . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_cvt_f64_f32_e32 v[6:7], v6<br>
+# CHECK-NEXT: [0,4] . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_cvt_u32_f64_e32 v8, v[8:9]<br>
+# CHECK-NEXT: [0,5] . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_cvt_f64_u32_e32 v[10:11], v10<br>
+# CHECK-NEXT: [0,6] . . . . . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_frexp_exp_i32_f64_e32 v0, v[0:1]<br>
+# CHECK-NEXT: [0,7] . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_frexp_mant_f64_e32 v[2:3], v[2:3]<br>
+# CHECK-NEXT: [0,8] . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_fract_f64_e32 v[4:5], v[4:5]<br>
+# CHECK-NEXT: [0,9] . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_trunc_f64_e32 v[0:1], v[0:1]<br>
+# CHECK-NEXT: [0,10] . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_ceil_f64_e32 v[2:3], v[2:3]<br>
+# CHECK-NEXT: [0,11] . . . . . . . . . .DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_rndne_f64_e32 v[4:5], v[4:5]<br>
+# CHECK-NEXT: [0,12] . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_floor_f64_e32 v[6:7], v[6:7]<br>
+# CHECK-NEXT: [0,13] . . . . . . . . . . . . . .DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . v_fma_f64 v[0:1], v[0:1], v[0:1], v[0:1]<br>
+# CHECK-NEXT: [0,14] . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . . . . . . . . . . . . . . . . . . . . . . . v_add_f64 v[2:3], v[2:3], v[2:3]<br>
+# CHECK-NEXT: [0,15] . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . v_mul_f64 v[4:5], v[4:5], v[4:5]<br>
+# CHECK-NEXT: [0,16] . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . v_min_f64 v[6:7], v[6:7], v[6:7]<br>
+# CHECK-NEXT: [0,17] . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . v_max_f64 v[8:9], v[8:9], v[8:9]<br>
+# CHECK-NEXT: [0,18] . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . . . . . v_div_fmas_f64 v[0:1], v[0:1], v[0:1], v[0:1]<br>
+# CHECK-NEXT: [0,19] . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . . . . . . . . . . v_div_fixup_f64 v[0:1], v[0:1], v[0:1], v[0:1]<br>
+# CHECK-NEXT: [0,20] . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . . . . . . . . . . v_ldexp_f64 v[2:3], v[2:3], v0<br>
+# CHECK-NEXT: [0,21] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . . . . . . v_div_scale_f64 v[0:1], vcc_lo, v[0:1], v[0:1], v[0:1]<br>
+# CHECK-NEXT: [0,22] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . v_trig_preop_f64 v[2:3], v[2:3], v0<br>
+# CHECK-NEXT: [0,23] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeE . . . . . . v_cmp_eq_f64_e32 vcc_lo, v[0:1], v[0:1]<br>
+# CHECK-NEXT: [0,24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DeeeeeeeeeeeeeeeeeeeeeE . . v_cmp_class_f64_e64 vcc_lo, v[2:3], s0<br>
+# CHECK-NEXT: [0,25] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeE . v_rcp_f64_e32 v[0:1], v[0:1]<br>
+# CHECK-NEXT: [0,26] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeE. v_rsq_f64_e32 v[2:3], v[2:3]<br>
+# CHECK-NEXT: [0,27] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeE v_sqrt_f64_e32 v[4:5], v[4:5]<br>
<br>
# CHECK: Average Wait times (based on the timeline view):<br>
# CHECK-NEXT: [0]: Executions<br>
<br>
diff --git a/llvm/test/tools/llvm-mca/AMDGPU/gfx9-retireooo.s b/llvm/test/tools/llvm-mca/AMDGPU/gfx9-retireooo.s<br>
deleted file mode 100644<br>
index 706ed36f9e98..000000000000<br>
--- a/llvm/test/tools/llvm-mca/AMDGPU/gfx9-retireooo.s<br>
+++ /dev/null<br>
@@ -1,233 +0,0 @@<br>
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py<br>
-# RUN: llvm-mca -mtriple=amdgcn -mcpu=gfx900 --timeline --iterations=1 --timeline-max-cycles=0 < %s | FileCheck %s<br>
-<br>
-s_load_dwordx2 s[2:3], s[0:1], 0x24<br>
-s_load_dwordx2 s[0:1], s[0:1], 0x2c<br>
-s_waitcnt lgkmcnt(0)<br>
-v_mov_b32_e32 v0, s2<br>
-v_mov_b32_e32 v1, s3<br>
-flat_load_dword v2, v[0:1]<br>
-flat_load_dword v3, v[0:1] offset:8<br>
-flat_load_dword v4, v[0:1] offset:16<br>
-flat_load_dword v5, v[0:1] offset:24<br>
-v_mov_b32_e32 v0, s0<br>
-v_mov_b32_e32 v1, s1<br>
-v_mov_b32_e32 v6, s6<br>
-v_mov_b32_e32 v7, s7<br>
-v_mov_b32_e32 v8, s8<br>
-v_mov_b32_e32 v9, s9<br>
-v_mov_b32_e32 v10, s10<br>
-v_mov_b32_e32 v11, s11<br>
-v_mov_b32_e32 v12, s12<br>
-v_mov_b32_e32 v13, s13<br>
-v_mov_b32_e32 v14, s14<br>
-v_mov_b32_e32 v15, s15<br>
-v_mov_b32_e32 v16, s16<br>
-v_mov_b32_e32 v17, s17<br>
-v_mov_b32_e32 v18, s18<br>
-v_mov_b32_e32 v19, s19<br>
-v_mov_b32_e32 v20, s20<br>
-v_mov_b32_e32 v21, s21<br>
-v_mov_b32_e32 v22, s22<br>
-v_mov_b32_e32 v23, s23<br>
-v_mov_b32_e32 v24, s24<br>
-v_mov_b32_e32 v25, s25<br>
-v_mov_b32_e32 v26, s26<br>
-v_mov_b32_e32 v27, s27<br>
-v_mov_b32_e32 v28, s28<br>
-v_mov_b32_e32 v29, s29<br>
-s_waitcnt vmcnt(0) lgkmcnt(0)<br>
-<br>
-# CHECK: Iterations: 1<br>
-# CHECK-NEXT: Instructions: 36<br>
-# CHECK-NEXT: Total Cycles: 94<br>
-# CHECK-NEXT: Total uOps: 36<br>
-<br>
-# CHECK: Dispatch Width: 1<br>
-# CHECK-NEXT: uOps Per Cycle: 0.38<br>
-# CHECK-NEXT: IPC: 0.38<br>
-# CHECK-NEXT: Block RThroughput: 36.0<br>
-<br>
-# CHECK: Instruction Info:<br>
-# CHECK-NEXT: [1]: #uOps<br>
-# CHECK-NEXT: [2]: Latency<br>
-# CHECK-NEXT: [3]: RThroughput<br>
-# CHECK-NEXT: [4]: MayLoad<br>
-# CHECK-NEXT: [5]: MayStore<br>
-# CHECK-NEXT: [6]: HasSideEffects (U)<br>
-<br>
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:<br>
-# CHECK-NEXT: 1 5 1.00 * s_load_dwordx2 s[2:3], s[0:1], 0x24<br>
-# CHECK-NEXT: 1 5 1.00 * s_load_dwordx2 s[0:1], s[0:1], 0x2c<br>
-# CHECK-NEXT: 1 1 1.00 U s_waitcnt lgkmcnt(0)<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v0, s2<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v1, s3<br>
-# CHECK-NEXT: 1 80 1.00 * U flat_load_dword v2, v[0:1]<br>
-# CHECK-NEXT: 1 80 1.00 * U flat_load_dword v3, v[0:1] offset:8<br>
-# CHECK-NEXT: 1 80 1.00 * U flat_load_dword v4, v[0:1] offset:16<br>
-# CHECK-NEXT: 1 80 1.00 * U flat_load_dword v5, v[0:1] offset:24<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v0, s0<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v1, s1<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v6, s6<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v7, s7<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v8, s8<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v9, s9<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v10, s10<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v11, s11<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v12, s12<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v13, s13<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v14, s14<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v15, s15<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v16, s16<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v17, s17<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v18, s18<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v19, s19<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v20, s20<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v21, s21<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v22, s22<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v23, s23<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v24, s24<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v25, s25<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v26, s26<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v27, s27<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v28, s28<br>
-# CHECK-NEXT: 1 1 1.00 U v_mov_b32_e32 v29, s29<br>
-# CHECK-NEXT: 1 1 1.00 U s_waitcnt vmcnt(0) lgkmcnt(0)<br>
-<br>
-# CHECK: Resources:<br>
-# CHECK-NEXT: [0] - HWBranch<br>
-# CHECK-NEXT: [1] - HWExport<br>
-# CHECK-NEXT: [2] - HWLGKM<br>
-# CHECK-NEXT: [3] - HWSALU<br>
-# CHECK-NEXT: [4] - HWVALU<br>
-# CHECK-NEXT: [5] - HWVMEM<br>
-# CHECK-NEXT: [6] - HWXDL<br>
-<br>
-# CHECK: Resource pressure per iteration:<br>
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6]<br>
-# CHECK-NEXT: - - 2.00 2.00 28.00 4.00 -<br>
-<br>
-# CHECK: Resource pressure by instruction:<br>
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] Instructions:<br>
-# CHECK-NEXT: - - 1.00 - - - - s_load_dwordx2 s[2:3], s[0:1], 0x24<br>
-# CHECK-NEXT: - - 1.00 - - - - s_load_dwordx2 s[0:1], s[0:1], 0x2c<br>
-# CHECK-NEXT: - - - 1.00 - - - s_waitcnt lgkmcnt(0)<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v0, s2<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v1, s3<br>
-# CHECK-NEXT: - - - - - 1.00 - flat_load_dword v2, v[0:1]<br>
-# CHECK-NEXT: - - - - - 1.00 - flat_load_dword v3, v[0:1] offset:8<br>
-# CHECK-NEXT: - - - - - 1.00 - flat_load_dword v4, v[0:1] offset:16<br>
-# CHECK-NEXT: - - - - - 1.00 - flat_load_dword v5, v[0:1] offset:24<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v0, s0<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v1, s1<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v6, s6<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v7, s7<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v8, s8<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v9, s9<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v10, s10<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v11, s11<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v12, s12<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v13, s13<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v14, s14<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v15, s15<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v16, s16<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v17, s17<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v18, s18<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v19, s19<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v20, s20<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v21, s21<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v22, s22<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v23, s23<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v24, s24<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v25, s25<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v26, s26<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v27, s27<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v28, s28<br>
-# CHECK-NEXT: - - - - 1.00 - - v_mov_b32_e32 v29, s29<br>
-# CHECK-NEXT: - - - 1.00 - - - s_waitcnt vmcnt(0) lgkmcnt(0)<br>
-<br>
-# CHECK: Timeline view:<br>
-# CHECK-NEXT: 0123456789 0123456789 0123456789 0123456789 0123<br>
-# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789 0123456789<br>
-<br>
-# CHECK: [0,0] DeeeeE . . . . . . . . . . . . . . . . . . s_load_dwordx2 s[2:3], s[0:1], 0x24<br>
-# CHECK-NEXT: [0,1] .DeeeeE . . . . . . . . . . . . . . . . . . s_load_dwordx2 s[0:1], s[0:1], 0x2c<br>
-# CHECK-NEXT: [0,2] . .DE . . . . . . . . . . . . . . . . . . s_waitcnt lgkmcnt(0)<br>
-# CHECK-NEXT: [0,3] . . DE . . . . . . . . . . . . . . . . . . v_mov_b32_e32 v0, s2<br>
-# CHECK-NEXT: [0,4] . . DE. . . . . . . . . . . . . . . . . . v_mov_b32_e32 v1, s3<br>
-# CHECK-NEXT: [0,5] . . DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeE. . flat_load_dword v2, v[0:1]<br>
-# CHECK-NEXT: [0,6] . . DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeE . flat_load_dword v3, v[0:1] offset:8<br>
-# CHECK-NEXT: [0,7] . . .DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeE . flat_load_dword v4, v[0:1] offset:16<br>
-# CHECK-NEXT: [0,8] . . . DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeE. flat_load_dword v5, v[0:1] offset:24<br>
-# CHECK-NEXT: [0,9] . . . DE. . . . . . . . . . . . . . . . . v_mov_b32_e32 v0, s0<br>
-# CHECK-NEXT: [0,10] . . . DE . . . . . . . . . . . . . . . . v_mov_b32_e32 v1, s1<br>
-# CHECK-NEXT: [0,11] . . . DE . . . . . . . . . . . . . . . . v_mov_b32_e32 v6, s6<br>
-# CHECK-NEXT: [0,12] . . . .DE . . . . . . . . . . . . . . . . v_mov_b32_e32 v7, s7<br>
-# CHECK-NEXT: [0,13] . . . . DE . . . . . . . . . . . . . . . . v_mov_b32_e32 v8, s8<br>
-# CHECK-NEXT: [0,14] . . . . DE. . . . . . . . . . . . . . . . v_mov_b32_e32 v9, s9<br>
-# CHECK-NEXT: [0,15] . . . . DE . . . . . . . . . . . . . . . v_mov_b32_e32 v10, s10<br>
-# CHECK-NEXT: [0,16] . . . . DE . . . . . . . . . . . . . . . v_mov_b32_e32 v11, s11<br>
-# CHECK-NEXT: [0,17] . . . . .DE . . . . . . . . . . . . . . . v_mov_b32_e32 v12, s12<br>
-# CHECK-NEXT: [0,18] . . . . . DE . . . . . . . . . . . . . . . v_mov_b32_e32 v13, s13<br>
-# CHECK-NEXT: [0,19] . . . . . DE. . . . . . . . . . . . . . . v_mov_b32_e32 v14, s14<br>
-# CHECK-NEXT: [0,20] . . . . . DE . . . . . . . . . . . . . . v_mov_b32_e32 v15, s15<br>
-# CHECK-NEXT: [0,21] . . . . . DE . . . . . . . . . . . . . . v_mov_b32_e32 v16, s16<br>
-# CHECK-NEXT: [0,22] . . . . . .DE . . . . . . . . . . . . . . v_mov_b32_e32 v17, s17<br>
-# CHECK-NEXT: [0,23] . . . . . . DE . . . . . . . . . . . . . . v_mov_b32_e32 v18, s18<br>
-# CHECK-NEXT: [0,24] . . . . . . DE. . . . . . . . . . . . . . v_mov_b32_e32 v19, s19<br>
-# CHECK-NEXT: [0,25] . . . . . . DE . . . . . . . . . . . . . v_mov_b32_e32 v20, s20<br>
-# CHECK-NEXT: [0,26] . . . . . . DE . . . . . . . . . . . . . v_mov_b32_e32 v21, s21<br>
-# CHECK-NEXT: [0,27] . . . . . . .DE . . . . . . . . . . . . . v_mov_b32_e32 v22, s22<br>
-# CHECK-NEXT: [0,28] . . . . . . . DE . . . . . . . . . . . . . v_mov_b32_e32 v23, s23<br>
-# CHECK-NEXT: [0,29] . . . . . . . DE. . . . . . . . . . . . . v_mov_b32_e32 v24, s24<br>
-# CHECK-NEXT: [0,30] . . . . . . . DE . . . . . . . . . . . . v_mov_b32_e32 v25, s25<br>
-# CHECK-NEXT: [0,31] . . . . . . . DE . . . . . . . . . . . . v_mov_b32_e32 v26, s26<br>
-# CHECK-NEXT: [0,32] . . . . . . . .DE . . . . . . . . . . . . v_mov_b32_e32 v27, s27<br>
-# CHECK-NEXT: [0,33] . . . . . . . . DE . . . . . . . . . . . . v_mov_b32_e32 v28, s28<br>
-# CHECK-NEXT: [0,34] . . . . . . . . DE. . . . . . . . . . . . v_mov_b32_e32 v29, s29<br>
-# CHECK-NEXT: [0,35] . . . . . . . . . . . . . . . . . . . DE s_waitcnt vmcnt(0) lgkmcnt(0)<br>
-<br>
-# CHECK: Average Wait times (based on the timeline view):<br>
-# CHECK-NEXT: [0]: Executions<br>
-# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue<br>
-# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready<br>
-# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage<br>
-<br>
-# CHECK: [0] [1] [2] [3]<br>
-# CHECK-NEXT: 0. 1 0.0 0.0 0.0 s_load_dwordx2 s[2:3], s[0:1], 0x24<br>
-# CHECK-NEXT: 1. 1 0.0 0.0 0.0 s_load_dwordx2 s[0:1], s[0:1], 0x2c<br>
-# CHECK-NEXT: 2. 1 0.0 0.0 0.0 s_waitcnt lgkmcnt(0)<br>
-# CHECK-NEXT: 3. 1 0.0 0.0 0.0 v_mov_b32_e32 v0, s2<br>
-# CHECK-NEXT: 4. 1 0.0 0.0 0.0 v_mov_b32_e32 v1, s3<br>
-# CHECK-NEXT: 5. 1 0.0 0.0 0.0 flat_load_dword v2, v[0:1]<br>
-# CHECK-NEXT: 6. 1 0.0 0.0 0.0 flat_load_dword v3, v[0:1] offset:8<br>
-# CHECK-NEXT: 7. 1 0.0 0.0 0.0 flat_load_dword v4, v[0:1] offset:16<br>
-# CHECK-NEXT: 8. 1 0.0 0.0 0.0 flat_load_dword v5, v[0:1] offset:24<br>
-# CHECK-NEXT: 9. 1 0.0 0.0 0.0 v_mov_b32_e32 v0, s0<br>
-# CHECK-NEXT: 10. 1 0.0 0.0 0.0 v_mov_b32_e32 v1, s1<br>
-# CHECK-NEXT: 11. 1 0.0 0.0 0.0 v_mov_b32_e32 v6, s6<br>
-# CHECK-NEXT: 12. 1 0.0 0.0 0.0 v_mov_b32_e32 v7, s7<br>
-# CHECK-NEXT: 13. 1 0.0 0.0 0.0 v_mov_b32_e32 v8, s8<br>
-# CHECK-NEXT: 14. 1 0.0 0.0 0.0 v_mov_b32_e32 v9, s9<br>
-# CHECK-NEXT: 15. 1 0.0 0.0 0.0 v_mov_b32_e32 v10, s10<br>
-# CHECK-NEXT: 16. 1 0.0 0.0 0.0 v_mov_b32_e32 v11, s11<br>
-# CHECK-NEXT: 17. 1 0.0 0.0 0.0 v_mov_b32_e32 v12, s12<br>
-# CHECK-NEXT: 18. 1 0.0 0.0 0.0 v_mov_b32_e32 v13, s13<br>
-# CHECK-NEXT: 19. 1 0.0 0.0 0.0 v_mov_b32_e32 v14, s14<br>
-# CHECK-NEXT: 20. 1 0.0 0.0 0.0 v_mov_b32_e32 v15, s15<br>
-# CHECK-NEXT: 21. 1 0.0 0.0 0.0 v_mov_b32_e32 v16, s16<br>
-# CHECK-NEXT: 22. 1 0.0 0.0 0.0 v_mov_b32_e32 v17, s17<br>
-# CHECK-NEXT: 23. 1 0.0 0.0 0.0 v_mov_b32_e32 v18, s18<br>
-# CHECK-NEXT: 24. 1 0.0 0.0 0.0 v_mov_b32_e32 v19, s19<br>
-# CHECK-NEXT: 25. 1 0.0 0.0 0.0 v_mov_b32_e32 v20, s20<br>
-# CHECK-NEXT: 26. 1 0.0 0.0 0.0 v_mov_b32_e32 v21, s21<br>
-# CHECK-NEXT: 27. 1 0.0 0.0 0.0 v_mov_b32_e32 v22, s22<br>
-# CHECK-NEXT: 28. 1 0.0 0.0 0.0 v_mov_b32_e32 v23, s23<br>
-# CHECK-NEXT: 29. 1 0.0 0.0 0.0 v_mov_b32_e32 v24, s24<br>
-# CHECK-NEXT: 30. 1 0.0 0.0 0.0 v_mov_b32_e32 v25, s25<br>
-# CHECK-NEXT: 31. 1 0.0 0.0 0.0 v_mov_b32_e32 v26, s26<br>
-# CHECK-NEXT: 32. 1 0.0 0.0 0.0 v_mov_b32_e32 v27, s27<br>
-# CHECK-NEXT: 33. 1 0.0 0.0 0.0 v_mov_b32_e32 v28, s28<br>
-# CHECK-NEXT: 34. 1 0.0 0.0 0.0 v_mov_b32_e32 v29, s29<br>
-# CHECK-NEXT: 35. 1 0.0 0.0 0.0 s_waitcnt vmcnt(0) lgkmcnt(0)<br>
-# CHECK-NEXT: 1 0.0 0.0 0.0 <total><br>
<br>
diff --git a/llvm/tools/llvm-mca/lib/AMDGPU/AMDGPUCustomBehaviour.cpp b/llvm/tools/llvm-mca/lib/AMDGPU/AMDGPUCustomBehaviour.cpp<br>
index 6ee77fa2b384..a655f3faf1bf 100644<br>
--- a/llvm/tools/llvm-mca/lib/AMDGPU/AMDGPUCustomBehaviour.cpp<br>
+++ b/llvm/tools/llvm-mca/lib/AMDGPU/AMDGPUCustomBehaviour.cpp<br>
@@ -19,311 +19,15 @@<br>
namespace llvm {<br>
namespace mca {<br>
<br>
-void AMDGPUInstrPostProcess::postProcessInstruction(<br>
- std::unique_ptr<Instruction> &Inst, const MCInst &MCI) {<br>
- switch (MCI.getOpcode()) {<br>
- case AMDGPU::S_WAITCNT:<br>
- case AMDGPU::S_WAITCNT_EXPCNT:<br>
- case AMDGPU::S_WAITCNT_LGKMCNT:<br>
- case AMDGPU::S_WAITCNT_VMCNT:<br>
- case AMDGPU::S_WAITCNT_VSCNT:<br>
- case AMDGPU::S_WAITCNT_EXPCNT_gfx10:<br>
- case AMDGPU::S_WAITCNT_LGKMCNT_gfx10:<br>
- case AMDGPU::S_WAITCNT_VMCNT_gfx10:<br>
- case AMDGPU::S_WAITCNT_VSCNT_gfx10:<br>
- case AMDGPU::S_WAITCNT_gfx10:<br>
- case AMDGPU::S_WAITCNT_gfx6_gfx7:<br>
- case AMDGPU::S_WAITCNT_vi:<br>
- return processWaitCnt(Inst, MCI);<br>
- }<br>
-}<br>
-<br>
-// s_waitcnt instructions encode important information as immediate operands<br>
-// which are lost during the MCInst -> mca::Instruction lowering.<br>
-void AMDGPUInstrPostProcess::processWaitCnt(std::unique_ptr<Instruction> &Inst,<br>
- const MCInst &MCI) {<br>
- for (int Idx = 0, N = MCI.size(); Idx < N; Idx++) {<br>
- MCAOperand Op;<br>
- const MCOperand &MCOp = MCI.getOperand(Idx);<br>
- if (MCOp.isReg()) {<br>
- Op = MCAOperand::createReg(MCOp.getReg());<br>
- } else if (MCOp.isImm()) {<br>
- Op = MCAOperand::createImm(MCOp.getImm());<br>
- }<br>
- Op.setIndex(Idx);<br>
- Inst->addOperand(Op);<br>
- }<br>
-}<br>
-<br>
AMDGPUCustomBehaviour::AMDGPUCustomBehaviour(const MCSubtargetInfo &STI,<br>
const SourceMgr &SrcMgr,<br>
const MCInstrInfo &MCII)<br>
- : CustomBehaviour(STI, SrcMgr, MCII) {<br>
- generateWaitCntInfo();<br>
-}<br>
+ : CustomBehaviour(STI, SrcMgr, MCII) {}<br>
<br>
unsigned AMDGPUCustomBehaviour::checkCustomHazard(ArrayRef<InstRef> IssuedInst,<br>
const InstRef &IR) {<br>
- const Instruction &Inst = *IR.getInstruction();<br>
- unsigned Opcode = Inst.getOpcode();<br>
-<br>
- // llvm-mca is generally run on fully compiled assembly so we wouldn't see any<br>
- // pseudo instructions here. However, there are plans for the future to make<br>
- // it possible to use mca within backend passes. As such, I have left the<br>
- // pseudo version of s_waitcnt within this switch statement.<br>
- switch (Opcode) {<br>
- default:<br>
- return 0;<br>
- case AMDGPU::S_WAITCNT: // This instruction<br>
- case AMDGPU::S_WAITCNT_EXPCNT:<br>
- case AMDGPU::S_WAITCNT_LGKMCNT:<br>
- case AMDGPU::S_WAITCNT_VMCNT:<br>
- case AMDGPU::S_WAITCNT_VSCNT: // to this instruction are all pseudo.<br>
- case AMDGPU::S_WAITCNT_EXPCNT_gfx10:<br>
- case AMDGPU::S_WAITCNT_LGKMCNT_gfx10:<br>
- case AMDGPU::S_WAITCNT_VMCNT_gfx10:<br>
- case AMDGPU::S_WAITCNT_VSCNT_gfx10:<br>
- case AMDGPU::S_WAITCNT_gfx10:<br>
- case AMDGPU::S_WAITCNT_gfx6_gfx7:<br>
- case AMDGPU::S_WAITCNT_vi:<br>
- // s_endpgm also behaves as if there is an implicit<br>
- // s_waitcnt 0, but I'm not sure if it would be appropriate<br>
- // to model this in llvm-mca based on how the iterations work<br>
- // while simulating the pipeline over and over.<br>
- return handleWaitCnt(IssuedInst, IR);<br>
- }<br>
-<br>
return 0;<br>
}<br>
<br>
-unsigned AMDGPUCustomBehaviour::handleWaitCnt(ArrayRef<InstRef> IssuedInst,<br>
- const InstRef &IR) {<br>
- // Currently, all s_waitcnt instructions are handled except s_waitcnt_depctr.<br>
- // I do not know how that instruction works so I did not attempt to model it.<br>
- // set the max values to begin<br>
- unsigned Vmcnt = 63;<br>
- unsigned Expcnt = 7;<br>
- unsigned Lgkmcnt = 31;<br>
- unsigned Vscnt = 63;<br>
- unsigned CurrVmcnt = 0;<br>
- unsigned CurrExpcnt = 0;<br>
- unsigned CurrLgkmcnt = 0;<br>
- unsigned CurrVscnt = 0;<br>
- unsigned CyclesToWaitVm = ~0U;<br>
- unsigned CyclesToWaitExp = ~0U;<br>
- unsigned CyclesToWaitLgkm = ~0U;<br>
- unsigned CyclesToWaitVs = ~0U;<br>
-<br>
- computeWaitCnt(IR, Vmcnt, Expcnt, Lgkmcnt, Vscnt);<br>
-<br>
- // We will now look at each of the currently executing instructions<br>
- // to find out if this wait instruction still needs to wait.<br>
- for (auto I = IssuedInst.begin(), E = IssuedInst.end(); I != E; I++) {<br>
- const InstRef &PrevIR = *I;<br>
- const Instruction &PrevInst = *PrevIR.getInstruction();<br>
- const unsigned PrevInstIndex = PrevIR.getSourceIndex() % SrcMgr.size();<br>
- const WaitCntInfo &PrevInstWaitInfo = InstrWaitCntInfo[PrevInstIndex];<br>
- const int CyclesLeft = PrevInst.getCyclesLeft();<br>
- assert(CyclesLeft != UNKNOWN_CYCLES &&<br>
- "We should know how many cycles are left for this instruction");<br>
- if (PrevInstWaitInfo.VmCnt) {<br>
- CurrVmcnt++;<br>
- if ((unsigned)CyclesLeft < CyclesToWaitVm)<br>
- CyclesToWaitVm = CyclesLeft;<br>
- }<br>
- if (PrevInstWaitInfo.ExpCnt) {<br>
- CurrExpcnt++;<br>
- if ((unsigned)CyclesLeft < CyclesToWaitExp)<br>
- CyclesToWaitExp = CyclesLeft;<br>
- }<br>
- if (PrevInstWaitInfo.LgkmCnt) {<br>
- CurrLgkmcnt++;<br>
- if ((unsigned)CyclesLeft < CyclesToWaitLgkm)<br>
- CyclesToWaitLgkm = CyclesLeft;<br>
- }<br>
- if (PrevInstWaitInfo.VsCnt) {<br>
- CurrVscnt++;<br>
- if ((unsigned)CyclesLeft < CyclesToWaitVs)<br>
- CyclesToWaitVs = CyclesLeft;<br>
- }<br>
- }<br>
-<br>
- unsigned CyclesToWait = ~0U;<br>
- if (CurrVmcnt > Vmcnt && CyclesToWaitVm < CyclesToWait)<br>
- CyclesToWait = CyclesToWaitVm;<br>
- if (CurrExpcnt > Expcnt && CyclesToWaitExp < CyclesToWait)<br>
- CyclesToWait = CyclesToWaitExp;<br>
- if (CurrLgkmcnt > Lgkmcnt && CyclesToWaitLgkm < CyclesToWait)<br>
- CyclesToWait = CyclesToWaitLgkm;<br>
- if (CurrVscnt > Vscnt && CyclesToWaitVs < CyclesToWait)<br>
- CyclesToWait = CyclesToWaitVs;<br>
-<br>
- // We may underestimate how many cycles we need to wait, but this<br>
- // isn't a big deal. Our return value is just how many cycles until<br>
- // this function gets run again. So as long as we don't overestimate<br>
- // the wait time, we'll still end up stalling at this instruction<br>
- // for the correct number of cycles.<br>
-<br>
- if (CyclesToWait == ~0U)<br>
- return 0;<br>
- return CyclesToWait;<br>
-}<br>
-<br>
-void AMDGPUCustomBehaviour::computeWaitCnt(const InstRef &IR, unsigned &Vmcnt,<br>
- unsigned &Expcnt, unsigned &Lgkmcnt,<br>
- unsigned &Vscnt) {<br>
- AMDGPU::IsaVersion IV = AMDGPU::getIsaVersion(STI.getCPU());<br>
- const Instruction &Inst = *IR.getInstruction();<br>
- unsigned Opcode = Inst.getOpcode();<br>
-<br>
- switch (Opcode) {<br>
- case AMDGPU::S_WAITCNT_EXPCNT_gfx10:<br>
- case AMDGPU::S_WAITCNT_LGKMCNT_gfx10:<br>
- case AMDGPU::S_WAITCNT_VMCNT_gfx10:<br>
- case AMDGPU::S_WAITCNT_VSCNT_gfx10: {<br>
- // Should probably be checking for nullptr<br>
- // here, but I'm not sure how I should handle the case<br>
- // where we see a nullptr.<br>
- const MCAOperand *OpReg = Inst.getOperand(0);<br>
- const MCAOperand *OpImm = Inst.getOperand(1);<br>
- assert(OpReg && OpReg->isReg() && "First operand should be a register.");<br>
- assert(OpImm && OpImm->isImm() && "Second operand should be an immediate.");<br>
- if (OpReg->getReg() != AMDGPU::SGPR_NULL) {<br>
- // Instruction is using a real register.<br>
- // Since we can't know what value this register will have,<br>
- // we can't compute what the value of this wait should be.<br>
- WithColor::warning() << "The register component of "<br>
- << MCII.getName(Opcode) << " will be completely "<br>
- << "ignored. So the wait may not be accurate.\n";<br>
- }<br>
- switch (Opcode) {<br>
- // Redundant switch so I don't have to repeat the code above<br>
- // for each case. There are more clever ways to avoid this<br>
- // extra switch and anyone can feel free to implement one of them.<br>
- case AMDGPU::S_WAITCNT_EXPCNT_gfx10:<br>
- Expcnt = OpImm->getImm();<br>
- break;<br>
- case AMDGPU::S_WAITCNT_LGKMCNT_gfx10:<br>
- Lgkmcnt = OpImm->getImm();<br>
- break;<br>
- case AMDGPU::S_WAITCNT_VMCNT_gfx10:<br>
- Vmcnt = OpImm->getImm();<br>
- break;<br>
- case AMDGPU::S_WAITCNT_VSCNT_gfx10:<br>
- Vscnt = OpImm->getImm();<br>
- break;<br>
- }<br>
- return;<br>
- }<br>
- case AMDGPU::S_WAITCNT_gfx10:<br>
- case AMDGPU::S_WAITCNT_gfx6_gfx7:<br>
- case AMDGPU::S_WAITCNT_vi:<br>
- unsigned WaitCnt = Inst.getOperand(0)->getImm();<br>
- AMDGPU::decodeWaitcnt(IV, WaitCnt, Vmcnt, Expcnt, Lgkmcnt);<br>
- return;<br>
- }<br>
-}<br>
-<br>
-void AMDGPUCustomBehaviour::generateWaitCntInfo() {<br>
- // The core logic from this function is taken from<br>
- // SIInsertWaitcnts::updateEventWaitcntAfter() In that pass, the instructions<br>
- // that are being looked at are in the MachineInstr format, whereas we have<br>
- // access to the MCInst format. The side effects of this are that we can't use<br>
- // the mayAccessVMEMThroughFlat(Inst) or mayAccessLDSThroughFlat(Inst)<br>
- // functions. Therefore, we conservatively assume that these functions will<br>
- // return true. This may cause a few instructions to be incorrectly tagged<br>
- // with an extra CNT. However, these are instructions that do interact with at<br>
- // least one CNT so giving them an extra CNT shouldn't cause issues in most<br>
- // scenarios.<br>
- AMDGPU::IsaVersion IV = AMDGPU::getIsaVersion(STI.getCPU());<br>
- InstrWaitCntInfo.resize(SrcMgr.size());<br>
-<br>
- int Index = 0;<br>
- for (auto I = SrcMgr.begin(), E = SrcMgr.end(); I != E; ++I, ++Index) {<br>
- const std::unique_ptr<Instruction> &Inst = *I;<br>
- unsigned Opcode = Inst->getOpcode();<br>
- const MCInstrDesc &MCID = MCII.get(Opcode);<br>
- if ((MCID.TSFlags & SIInstrFlags::DS) &&<br>
- (MCID.TSFlags & SIInstrFlags::LGKM_CNT)) {<br>
- InstrWaitCntInfo[Index].LgkmCnt = true;<br>
- if (isAlwaysGDS(Opcode) || hasModifiersSet(Inst, AMDGPU::OpName::gds))<br>
- InstrWaitCntInfo[Index].ExpCnt = true;<br>
- } else if (MCID.TSFlags & SIInstrFlags::FLAT) {<br>
- // We conservatively assume that mayAccessVMEMThroughFlat(Inst)<br>
- // and mayAccessLDSThroughFlat(Inst) would both return true for this<br>
- // instruction. We have to do this because those functions use<br>
- // information about the memory operands that we don't have access to.<br>
- InstrWaitCntInfo[Index].LgkmCnt = true;<br>
- if (!STI.hasFeature(AMDGPU::FeatureVscnt))<br>
- InstrWaitCntInfo[Index].VmCnt = true;<br>
- else if (MCID.mayLoad() && !(MCID.TSFlags & SIInstrFlags::IsAtomicNoRet))<br>
- InstrWaitCntInfo[Index].VmCnt = true;<br>
- else<br>
- InstrWaitCntInfo[Index].VsCnt = true;<br>
- } else if (isVMEM(MCID) && !AMDGPU::getMUBUFIsBufferInv(Opcode)) {<br>
- if (!STI.hasFeature(AMDGPU::FeatureVscnt))<br>
- InstrWaitCntInfo[Index].VmCnt = true;<br>
- else if ((MCID.mayLoad() &&<br>
- !(MCID.TSFlags & SIInstrFlags::IsAtomicNoRet)) ||<br>
- ((MCID.TSFlags & SIInstrFlags::MIMG) && !MCID.mayLoad() &&<br>
- !MCID.mayStore()))<br>
- InstrWaitCntInfo[Index].VmCnt = true;<br>
- else if (MCID.mayStore())<br>
- InstrWaitCntInfo[Index].VsCnt = true;<br>
-<br>
- // (IV.Major < 7) is meant to represent<br>
- // GCNTarget.vmemWriteNeedsExpWaitcnt()<br>
- // which is defined as<br>
- // { return getGeneration() < SEA_ISLANDS; }<br>
- if (IV.Major < 7 &&<br>
- (MCID.mayStore() || (MCID.TSFlags & SIInstrFlags::IsAtomicRet)))<br>
- InstrWaitCntInfo[Index].ExpCnt = true;<br>
- } else if (MCID.TSFlags & SIInstrFlags::SMRD) {<br>
- InstrWaitCntInfo[Index].LgkmCnt = true;<br>
- } else if (MCID.TSFlags & SIInstrFlags::EXP) {<br>
- InstrWaitCntInfo[Index].ExpCnt = true;<br>
- } else {<br>
- switch (Opcode) {<br>
- case AMDGPU::S_SENDMSG:<br>
- case AMDGPU::S_SENDMSGHALT:<br>
- case AMDGPU::S_MEMTIME:<br>
- case AMDGPU::S_MEMREALTIME:<br>
- InstrWaitCntInfo[Index].LgkmCnt = true;<br>
- break;<br>
- }<br>
- }<br>
- }<br>
-}<br>
-<br>
-// taken from SIInstrInfo::isVMEM()<br>
-bool AMDGPUCustomBehaviour::isVMEM(const MCInstrDesc &MCID) {<br>
- return MCID.TSFlags & SIInstrFlags::MUBUF ||<br>
- MCID.TSFlags & SIInstrFlags::MTBUF ||<br>
- MCID.TSFlags & SIInstrFlags::MIMG;<br>
-}<br>
-<br>
-// taken from SIInstrInfo::hasModifiersSet()<br>
-bool AMDGPUCustomBehaviour::hasModifiersSet(<br>
- const std::unique_ptr<Instruction> &Inst, unsigned OpName) const {<br>
- int Idx = AMDGPU::getNamedOperandIdx(Inst->getOpcode(), OpName);<br>
- if (Idx == -1)<br>
- return false;<br>
-<br>
- const MCAOperand *Op = Inst->getOperand(Idx);<br>
- if (Op == nullptr || !Op->isImm() || !Op->getImm())<br>
- return false;<br>
-<br>
- return true;<br>
-}<br>
-<br>
-// taken from SIInstrInfo::isAlwaysGDS()<br>
-bool AMDGPUCustomBehaviour::isAlwaysGDS(uint16_t Opcode) const {<br>
- return Opcode == AMDGPU::DS_ORDERED_COUNT || Opcode == AMDGPU::DS_GWS_INIT ||<br>
- Opcode == AMDGPU::DS_GWS_SEMA_V || Opcode == AMDGPU::DS_GWS_SEMA_BR ||<br>
- Opcode == AMDGPU::DS_GWS_SEMA_P ||<br>
- Opcode == AMDGPU::DS_GWS_SEMA_RELEASE_ALL ||<br>
- Opcode == AMDGPU::DS_GWS_BARRIER;<br>
-}<br>
-<br>
} // namespace mca<br>
} // namespace llvm<br>
<br>
diff --git a/llvm/tools/llvm-mca/lib/AMDGPU/AMDGPUCustomBehaviour.h b/llvm/tools/llvm-mca/lib/AMDGPU/AMDGPUCustomBehaviour.h<br>
index e1efafa427fd..0dd21c7b4c44 100644<br>
--- a/llvm/tools/llvm-mca/lib/AMDGPU/AMDGPUCustomBehaviour.h<br>
+++ b/llvm/tools/llvm-mca/lib/AMDGPU/AMDGPUCustomBehaviour.h<br>
@@ -23,8 +23,6 @@ namespace llvm {<br>
namespace mca {<br>
<br>
class AMDGPUInstrPostProcess : public InstrPostProcess {<br>
- void processWaitCnt(std::unique_ptr<Instruction> &Inst, const MCInst &MCI);<br>
-<br>
public:<br>
AMDGPUInstrPostProcess(const MCSubtargetInfo &STI, const MCInstrInfo &MCII)<br>
: InstrPostProcess(STI, MCII) {}<br>
@@ -32,54 +30,10 @@ class AMDGPUInstrPostProcess : public InstrPostProcess {<br>
~AMDGPUInstrPostProcess() {}<br>
<br>
void postProcessInstruction(std::unique_ptr<Instruction> &Inst,<br>
- const MCInst &MCI) override;<br>
-};<br>
-<br>
-struct WaitCntInfo {<br>
- bool VmCnt = false;<br>
- bool ExpCnt = false;<br>
- bool LgkmCnt = false;<br>
- bool VsCnt = false;<br>
+ const MCInst &MCI) override {}<br>
};<br>
<br>
class AMDGPUCustomBehaviour : public CustomBehaviour {<br>
- /// Whenever MCA would like to dispatch an s_waitcnt instructions,<br>
- /// we must check all the instruction that are still executing to see if<br>
- /// they modify the same CNT as we need to wait for. This vector<br>
- /// gets built in the constructor and contains 1 WaitCntInfo struct<br>
- /// for each instruction within the SrcManager. Each element<br>
- /// tells us which CNTs that instruction may interact with.<br>
- /// We conservatively assume some instructions interact with more<br>
- /// CNTs than they do in reality, so we will occasionally wait<br>
- /// longer than necessary, but we shouldn't ever wait for shorter.<br>
- std::vector<WaitCntInfo> InstrWaitCntInfo;<br>
-<br>
- /// This method gets called from the constructor and is<br>
- /// where we setup the InstrWaitCntInfo vector.<br>
- /// The core logic for determining which CNTs an instruction<br>
- /// interacts with is taken from SIInsertWaitcnts::updateEventWaitcntAfter().<br>
- /// Unfortunately, some of the logic from that function is not avalable to us<br>
- /// in this scope so we conservatively end up assuming that some<br>
- /// instructions interact with more CNTs than they do in reality.<br>
- void generateWaitCntInfo();<br>
- /// Helper function used in generateWaitCntInfo()<br>
- bool hasModifiersSet(const std::unique_ptr<Instruction> &Inst,<br>
- unsigned OpName) const;<br>
- /// Helper function used in generateWaitCntInfo()<br>
- bool isAlwaysGDS(uint16_t Opcode) const;<br>
- /// Helper function used in generateWaitCntInfo()<br>
- bool isVMEM(const MCInstrDesc &MCID);<br>
- /// This method gets called from checkCustomHazard when mca is attempting to<br>
- /// dispatch an s_waitcnt instruction (or one of its variants). The method<br>
- /// looks at each of the instructions that are still executing in the pipeline<br>
- /// to determine if the waitcnt should force a wait.<br>
- unsigned handleWaitCnt(ArrayRef<InstRef> IssuedInst, const InstRef &IR);<br>
- /// Based on the type of s_waitcnt instruction we are looking at, and what its<br>
- /// operands are, this method will set the values for each of the cnt<br>
- /// references provided as arguments.<br>
- void computeWaitCnt(const InstRef &IR, unsigned &Vmcnt, unsigned &Expcnt,<br>
- unsigned &Lgkmcnt, unsigned &Vscnt);<br>
-<br>
public:<br>
AMDGPUCustomBehaviour(const MCSubtargetInfo &STI, const SourceMgr &SrcMgr,<br>
const MCInstrInfo &MCII);<br>
<br>
<br>
<br>
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