<div dir="ltr">Hi Max,<div><br></div><div>this patch broke arm bots which are not building X86 targets, I've committed </div><div>38f28f4621ed0a06347a89f2743d49c4a611d0a7 to fix it.<br></div><div><br></div><div>Cheers,</div><div>Yvan</div><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Fri, 5 Feb 2021 at 08:05, Max Kazantsev via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
Author: Max Kazantsev<br>
Date: 2021-02-05T14:04:29+07:00<br>
New Revision: 6c097f73ca032e73b2eb4ec21ee9d0773c86d4ed<br>
<br>
URL: <a href="https://github.com/llvm/llvm-project/commit/6c097f73ca032e73b2eb4ec21ee9d0773c86d4ed" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/6c097f73ca032e73b2eb4ec21ee9d0773c86d4ed</a><br>
DIFF: <a href="https://github.com/llvm/llvm-project/commit/6c097f73ca032e73b2eb4ec21ee9d0773c86d4ed.diff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/6c097f73ca032e73b2eb4ec21ee9d0773c86d4ed.diff</a><br>
<br>
LOG: [Test] Add more tests demonstrating oddities in behavior of LSR<br>
<br>
These tests demonstrate that LSR does not insert IV increment<br>
into the latch block (as it supposes to) when it can use an<br>
existing Phi as IV rather than creating a new LSR IV.<br>
<br>
Added: <br>
llvm/test/Transforms/LoopStrengthReduce/post-increment-insertion.ll<br>
<br>
Modified: <br>
llvm/test/CodeGen/X86/2020_12_02_decrementing_loop.ll<br>
<br>
Removed: <br>
<br>
<br>
<br>
################################################################################<br>
diff --git a/llvm/test/CodeGen/X86/2020_12_02_decrementing_loop.ll b/llvm/test/CodeGen/X86/2020_12_02_decrementing_loop.ll<br>
index 510301d9b3b3..5d860ea6e98e 100644<br>
--- a/llvm/test/CodeGen/X86/2020_12_02_decrementing_loop.ll<br>
+++ b/llvm/test/CodeGen/X86/2020_12_02_decrementing_loop.ll<br>
@@ -2,8 +2,8 @@<br>
; RUN: llc < %s -mtriple=x86_64-apple-macosx | FileCheck %s<br>
<br>
; TODO: We can get rid of movq here by using <br>
diff erent offset and %rax.<br>
-define i32 @test(i32* %p, i64 %len, i32 %x) {<br>
-; CHECK-LABEL: test:<br>
+define i32 @test_01(i32* %p, i64 %len, i32 %x) {<br>
+; CHECK-LABEL: test_01:<br>
; CHECK: ## %bb.0: ## %entry<br>
; CHECK-NEXT: movq %rsi, %rax<br>
; CHECK-NEXT: .p2align 4, 0x90<br>
@@ -42,3 +42,89 @@ exit: ; preds = %loop<br>
failure: ; preds = %backedge<br>
unreachable<br>
}<br>
+<br>
+define i32 @test_02(i32* %p, i64 %len, i32 %x) {<br>
+; CHECK-LABEL: test_02:<br>
+; CHECK: ## %bb.0: ## %entry<br>
+; CHECK-NEXT: .p2align 4, 0x90<br>
+; CHECK-NEXT: LBB1_1: ## %loop<br>
+; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1<br>
+; CHECK-NEXT: testq %rsi, %rsi<br>
+; CHECK-NEXT: je LBB1_4<br>
+; CHECK-NEXT: ## %bb.2: ## %backedge<br>
+; CHECK-NEXT: ## in Loop: Header=BB1_1 Depth=1<br>
+; CHECK-NEXT: cmpl %edx, -4(%rdi,%rsi,4)<br>
+; CHECK-NEXT: leaq -1(%rsi), %rsi<br>
+; CHECK-NEXT: jne LBB1_1<br>
+; CHECK-NEXT: ## %bb.3: ## %failure<br>
+; CHECK-NEXT: ud2<br>
+; CHECK-NEXT: LBB1_4: ## %exit<br>
+; CHECK-NEXT: movl $-1, %eax<br>
+; CHECK-NEXT: retq<br>
+entry:<br>
+ %start = add i64 %len, -1<br>
+ br label %loop<br>
+<br>
+loop: ; preds = %backedge, %entry<br>
+ %iv = phi i64 [ %iv.next, %backedge ], [ %start, %entry ]<br>
+ %iv.next = add nsw i64 %iv, -1<br>
+ %iv.offset = add i64 %iv, 1<br>
+ %iv.next.offset = add i64 %iv.next, 1<br>
+ %cond_1 = icmp eq i64 %iv.offset, 0<br>
+ br i1 %cond_1, label %exit, label %backedge<br>
+<br>
+backedge: ; preds = %loop<br>
+ %addr = getelementptr inbounds i32, i32* %p, i64 %iv.next.offset<br>
+ %loaded = load atomic i32, i32* %addr unordered, align 4<br>
+ %cond_2 = icmp eq i32 %loaded, %x<br>
+ br i1 %cond_2, label %failure, label %loop<br>
+<br>
+exit: ; preds = %loop<br>
+ ret i32 -1<br>
+<br>
+failure: ; preds = %backedge<br>
+ unreachable<br>
+}<br>
+<br>
+define i32 @test_03(i32* %p, i64 %len, i32 %x) {<br>
+; CHECK-LABEL: test_03:<br>
+; CHECK: ## %bb.0: ## %entry<br>
+; CHECK-NEXT: .p2align 4, 0x90<br>
+; CHECK-NEXT: LBB2_1: ## %loop<br>
+; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1<br>
+; CHECK-NEXT: testq %rsi, %rsi<br>
+; CHECK-NEXT: je LBB2_4<br>
+; CHECK-NEXT: ## %bb.2: ## %backedge<br>
+; CHECK-NEXT: ## in Loop: Header=BB2_1 Depth=1<br>
+; CHECK-NEXT: cmpl %edx, -4(%rdi,%rsi,4)<br>
+; CHECK-NEXT: leaq -1(%rsi), %rsi<br>
+; CHECK-NEXT: jne LBB2_1<br>
+; CHECK-NEXT: ## %bb.3: ## %failure<br>
+; CHECK-NEXT: ud2<br>
+; CHECK-NEXT: LBB2_4: ## %exit<br>
+; CHECK-NEXT: movl $-1, %eax<br>
+; CHECK-NEXT: retq<br>
+entry:<br>
+ %start = add i64 %len, -100<br>
+ br label %loop<br>
+<br>
+loop: ; preds = %backedge, %entry<br>
+ %iv = phi i64 [ %iv.next, %backedge ], [ %start, %entry ]<br>
+ %iv.next = add nsw i64 %iv, -1<br>
+ %iv.offset = add i64 %iv, 100<br>
+ %iv.next.offset = add i64 %iv.next, 100<br>
+ %cond_1 = icmp eq i64 %iv.offset, 0<br>
+ br i1 %cond_1, label %exit, label %backedge<br>
+<br>
+backedge: ; preds = %loop<br>
+ %addr = getelementptr inbounds i32, i32* %p, i64 %iv.next.offset<br>
+ %loaded = load atomic i32, i32* %addr unordered, align 4<br>
+ %cond_2 = icmp eq i32 %loaded, %x<br>
+ br i1 %cond_2, label %failure, label %loop<br>
+<br>
+exit: ; preds = %loop<br>
+ ret i32 -1<br>
+<br>
+failure: ; preds = %backedge<br>
+ unreachable<br>
+}<br>
<br>
diff --git a/llvm/test/Transforms/LoopStrengthReduce/post-increment-insertion.ll b/llvm/test/Transforms/LoopStrengthReduce/post-increment-insertion.ll<br>
new file mode 100644<br>
index 000000000000..d7fa20803f87<br>
--- /dev/null<br>
+++ b/llvm/test/Transforms/LoopStrengthReduce/post-increment-insertion.ll<br>
@@ -0,0 +1,138 @@<br>
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py<br>
+; RUN: opt < %s -loop-reduce -S | FileCheck %s<br>
+<br>
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2"<br>
+target triple = "x86_64-unknown-linux-gnu"<br>
+<br>
+; FIXME: iv.next is supposed to be inserted in the backedge.<br>
+define i32 @test_01(i32* %p, i64 %len, i32 %x) {<br>
+; CHECK-LABEL: @test_01(<br>
+; CHECK-NEXT: entry:<br>
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i32, i32* [[P:%.*]], i64 -1<br>
+; CHECK-NEXT: br label [[LOOP:%.*]]<br>
+; CHECK: loop:<br>
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]<br>
+; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], -1<br>
+; CHECK-NEXT: [[COND_1:%.*]] = icmp eq i64 [[IV]], 0<br>
+; CHECK-NEXT: br i1 [[COND_1]], label [[EXIT:%.*]], label [[BACKEDGE]]<br>
+; CHECK: backedge:<br>
+; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i32, i32* [[SCEVGEP]], i64 [[IV]]<br>
+; CHECK-NEXT: [[LOADED:%.*]] = load atomic i32, i32* [[SCEVGEP1]] unordered, align 4<br>
+; CHECK-NEXT: [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]<br>
+; CHECK-NEXT: br i1 [[COND_2]], label [[FAILURE:%.*]], label [[LOOP]]<br>
+; CHECK: exit:<br>
+; CHECK-NEXT: ret i32 -1<br>
+; CHECK: failure:<br>
+; CHECK-NEXT: unreachable<br>
+;<br>
+entry:<br>
+ br label %loop<br>
+<br>
+loop: ; preds = %backedge, %entry<br>
+ %iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ]<br>
+ %iv.next = add nsw i64 %iv, -1<br>
+ %cond_1 = icmp eq i64 %iv, 0<br>
+ br i1 %cond_1, label %exit, label %backedge<br>
+<br>
+backedge: ; preds = %loop<br>
+ %addr = getelementptr inbounds i32, i32* %p, i64 %iv.next<br>
+ %loaded = load atomic i32, i32* %addr unordered, align 4<br>
+ %cond_2 = icmp eq i32 %loaded, %x<br>
+ br i1 %cond_2, label %failure, label %loop<br>
+<br>
+exit: ; preds = %loop<br>
+ ret i32 -1<br>
+<br>
+failure: ; preds = %backedge<br>
+ unreachable<br>
+}<br>
+<br>
+define i32 @test_02(i32* %p, i64 %len, i32 %x) {<br>
+; CHECK-LABEL: @test_02(<br>
+; CHECK-NEXT: entry:<br>
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i32, i32* [[P:%.*]], i64 -1<br>
+; CHECK-NEXT: br label [[LOOP:%.*]]<br>
+; CHECK: loop:<br>
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]<br>
+; CHECK-NEXT: [[COND_1:%.*]] = icmp eq i64 [[LSR_IV]], 0<br>
+; CHECK-NEXT: br i1 [[COND_1]], label [[EXIT:%.*]], label [[BACKEDGE]]<br>
+; CHECK: backedge:<br>
+; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i32, i32* [[SCEVGEP]], i64 [[LSR_IV]]<br>
+; CHECK-NEXT: [[LOADED:%.*]] = load atomic i32, i32* [[SCEVGEP1]] unordered, align 4<br>
+; CHECK-NEXT: [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]<br>
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], -1<br>
+; CHECK-NEXT: br i1 [[COND_2]], label [[FAILURE:%.*]], label [[LOOP]]<br>
+; CHECK: exit:<br>
+; CHECK-NEXT: ret i32 -1<br>
+; CHECK: failure:<br>
+; CHECK-NEXT: unreachable<br>
+;<br>
+entry:<br>
+ %start = add i64 %len, -1<br>
+ br label %loop<br>
+<br>
+loop: ; preds = %backedge, %entry<br>
+ %iv = phi i64 [ %iv.next, %backedge ], [ %start, %entry ]<br>
+ %iv.next = add nsw i64 %iv, -1<br>
+ %iv.offset = add i64 %iv, 1<br>
+ %iv.next.offset = add i64 %iv.next, 1<br>
+ %cond_1 = icmp eq i64 %iv.offset, 0<br>
+ br i1 %cond_1, label %exit, label %backedge<br>
+<br>
+backedge: ; preds = %loop<br>
+ %addr = getelementptr inbounds i32, i32* %p, i64 %iv.next.offset<br>
+ %loaded = load atomic i32, i32* %addr unordered, align 4<br>
+ %cond_2 = icmp eq i32 %loaded, %x<br>
+ br i1 %cond_2, label %failure, label %loop<br>
+<br>
+exit: ; preds = %loop<br>
+ ret i32 -1<br>
+<br>
+failure: ; preds = %backedge<br>
+ unreachable<br>
+}<br>
+<br>
+define i32 @test_03(i32* %p, i64 %len, i32 %x) {<br>
+; CHECK-LABEL: @test_03(<br>
+; CHECK-NEXT: entry:<br>
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i32, i32* [[P:%.*]], i64 -1<br>
+; CHECK-NEXT: br label [[LOOP:%.*]]<br>
+; CHECK: loop:<br>
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]<br>
+; CHECK-NEXT: [[COND_1:%.*]] = icmp eq i64 [[LSR_IV]], 0<br>
+; CHECK-NEXT: br i1 [[COND_1]], label [[EXIT:%.*]], label [[BACKEDGE]]<br>
+; CHECK: backedge:<br>
+; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i32, i32* [[SCEVGEP]], i64 [[LSR_IV]]<br>
+; CHECK-NEXT: [[LOADED:%.*]] = load atomic i32, i32* [[SCEVGEP1]] unordered, align 4<br>
+; CHECK-NEXT: [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]<br>
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], -1<br>
+; CHECK-NEXT: br i1 [[COND_2]], label [[FAILURE:%.*]], label [[LOOP]]<br>
+; CHECK: exit:<br>
+; CHECK-NEXT: ret i32 -1<br>
+; CHECK: failure:<br>
+; CHECK-NEXT: unreachable<br>
+;<br>
+entry:<br>
+ %start = add i64 %len, -100<br>
+ br label %loop<br>
+<br>
+loop: ; preds = %backedge, %entry<br>
+ %iv = phi i64 [ %iv.next, %backedge ], [ %start, %entry ]<br>
+ %iv.next = add nsw i64 %iv, -1<br>
+ %iv.offset = add i64 %iv, 100<br>
+ %iv.next.offset = add i64 %iv.next, 100<br>
+ %cond_1 = icmp eq i64 %iv.offset, 0<br>
+ br i1 %cond_1, label %exit, label %backedge<br>
+<br>
+backedge: ; preds = %loop<br>
+ %addr = getelementptr inbounds i32, i32* %p, i64 %iv.next.offset<br>
+ %loaded = load atomic i32, i32* %addr unordered, align 4<br>
+ %cond_2 = icmp eq i32 %loaded, %x<br>
+ br i1 %cond_2, label %failure, label %loop<br>
+<br>
+exit: ; preds = %loop<br>
+ ret i32 -1<br>
+<br>
+failure: ; preds = %backedge<br>
+ unreachable<br>
+}<br>
<br>
<br>
<br>
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</blockquote></div>