<html><head><meta http-equiv="Content-Type" content="text/html; charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class="">To close the loop, I put up <a href="https://reviews.llvm.org/D96015" class="">https://reviews.llvm.org/D96015</a> with a potential fix.<br class=""><div><br class=""><blockquote type="cite" class=""><div class="">On Feb 4, 2021, at 11:04, Florian Hahn <<a href="mailto:florian_hahn@apple.com" class="">florian_hahn@apple.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class=""><br class="">Hi Matt,<br class=""><br class=""><br class="">We are seeing an issue where regallocfast runs out of registers with `llc -O0 -verify-machineinstrs` on X86 on the snippet below. Any ideas what could be going wrong here?<br class=""><br class=""><br class="">target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"<br class="">target triple = "x86_64-unknown-linux"<br class=""><br class="">define void @widget(i32* %arg, i1 %arg1) align 2 personality i8* undef {<br class="">bb:<br class=""> br i1 %arg1, label %bb2, label %bb3<br class=""><br class="">bb2: ; preds = %bb<br class=""> %tmp = alloca i8, i64 6144, align 32<br class=""> br label %bb3<br class=""><br class="">bb3: ; preds = %bb2, %bb<br class=""> %tmp4 = load i32, i32* %arg, align 4<br class=""> br label %bb5<br class=""><br class="">bb5: ; preds = %bb3<br class=""> %tmp6 = lshr i32 %tmp4, 8<br class=""> %tmp7 = and i32 %tmp6, 255<br class=""> invoke void (i8*, i32, i8*, ...) @baz(i8* undef, i32 3427, i8* undef, double undef, double undef, i32 undef, i32 %tmp7)<br class=""> to label %bb8 unwind label %bb9<br class=""><br class="">bb8: ; preds = %bb5<br class=""> ret void<br class=""><br class="">bb9: ; preds = %bb5<br class=""> %tmp10 = landingpad { i8*, i32 }<br class=""> cleanup<br class=""> ret void<br class="">}<br class=""><br class="">declare void @baz(i8*, i32, i8*, …)<br class=""><br class=""><br class="">`llc -O0 -verify-machineinstrs` produces:<br class=""><br class="">error: ran out of registers during register allocation<br class=""><br class=""><blockquote type="cite" class="">On Sep 30, 2020, at 15:35, Matt Arsenault via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:<br class=""><br class=""><br class="">Author: Matt Arsenault<br class="">Date: 2020-09-30T10:35:25-04:00<br class="">New Revision: 89baeaef2fa9a2441d087a218ac82e11a5d4e548<br class=""><br class="">URL: <a href="https://github.com/llvm/llvm-project/commit/89baeaef2fa9a2441d087a218ac82e11a5d4e548" class="">https://github.com/llvm/llvm-project/commit/89baeaef2fa9a2441d087a218ac82e11a5d4e548</a><br class="">DIFF: <a href="https://github.com/llvm/llvm-project/commit/89baeaef2fa9a2441d087a218ac82e11a5d4e548.diff" class="">https://github.com/llvm/llvm-project/commit/89baeaef2fa9a2441d087a218ac82e11a5d4e548.diff</a><br class=""><br class="">LOG: Reapply "RegAllocFast: Rewrite and improve"<br class=""><br class="">This reverts commit 73a6a164b84a8195defbb8f5eeb6faecfc478ad4.<br class=""><br class="">Added: <br class=""> llvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir<br class=""> llvm/test/CodeGen/AMDGPU/fastregalloc-illegal-subreg-physreg.mir<br class=""> llvm/test/CodeGen/AMDGPU/unexpected-reg-unit-state.mir<br class=""> llvm/test/CodeGen/PowerPC/spill-nor0.mir<br class=""> llvm/test/CodeGen/X86/bug47278-eflags-error.mir<br class=""> llvm/test/CodeGen/X86/bug47278.mir<br class=""><br class="">Modified: <br class=""> lldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp<br class=""> llvm/lib/CodeGen/RegAllocFast.cpp<br class=""> llvm/test/CodeGen/AArch64/GlobalISel/builtin-return-address-pacret.ll<br class=""> llvm/test/CodeGen/AArch64/GlobalISel/darwin-tls-call-clobber.ll<br class=""> llvm/test/CodeGen/AArch64/arm64-fast-isel-br.ll<br class=""> llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll<br class=""> llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll<br class=""> llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll<br class=""> llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll<br class=""> llvm/test/CodeGen/AArch64/arm64_32-fastisel.ll<br class=""> llvm/test/CodeGen/AArch64/arm64_32-null.ll<br class=""> llvm/test/CodeGen/AArch64/br-cond-not-merge.ll<br class=""> llvm/test/CodeGen/AArch64/cmpxchg-O0.ll<br class=""> llvm/test/CodeGen/AArch64/combine-loads.ll<br class=""> llvm/test/CodeGen/AArch64/fast-isel-cmpxchg.ll<br class=""> llvm/test/CodeGen/AArch64/popcount.ll<br class=""> llvm/test/CodeGen/AArch64/swift-return.ll<br class=""> llvm/test/CodeGen/AArch64/swifterror.ll<br class=""> llvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir<br class=""> llvm/test/CodeGen/AArch64/unwind-preserved.ll<br class=""> llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm.ll<br class=""> llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll<br class=""> llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir<br class=""> llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll<br class=""> llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll<br class=""> llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll<br class=""> llvm/test/CodeGen/AMDGPU/reserve-vgpr-for-sgpr-spill.ll<br class=""> llvm/test/CodeGen/AMDGPU/spill-agpr.mir<br class=""> llvm/test/CodeGen/AMDGPU/spill-m0.ll<br class=""> llvm/test/CodeGen/AMDGPU/spill192.mir<br class=""> llvm/test/CodeGen/AMDGPU/wwm-reserved.ll<br class=""> llvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll<br class=""> llvm/test/CodeGen/ARM/Windows/alloca.ll<br class=""> llvm/test/CodeGen/ARM/cmpxchg-O0-be.ll<br class=""> llvm/test/CodeGen/ARM/cmpxchg-O0.ll<br class=""> llvm/test/CodeGen/ARM/crash-greedy-v6.ll<br class=""> llvm/test/CodeGen/ARM/debug-info-blocks.ll<br class=""> llvm/test/CodeGen/ARM/fast-isel-call.ll<br class=""> llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll<br class=""> llvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll<br class=""> llvm/test/CodeGen/ARM/fast-isel-select.ll<br class=""> llvm/test/CodeGen/ARM/fast-isel-vararg.ll<br class=""> llvm/test/CodeGen/ARM/ldrd.ll<br class=""> llvm/test/CodeGen/ARM/legalize-bitcast.ll<br class=""> llvm/test/CodeGen/ARM/pr47454.ll<br class=""> llvm/test/CodeGen/ARM/stack-guard-reassign.ll<br class=""> llvm/test/CodeGen/ARM/swifterror.ll<br class=""> llvm/test/CodeGen/ARM/thumb-big-stack.ll<br class=""> llvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll<br class=""> llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll<br class=""> llvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll<br class=""> llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/aggregate_struct_return.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/brindirect.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/call.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctlz.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctpop.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/cttz.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/dyn_stackalloc.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_constants.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address_pic.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_split_because_of_memsize_or_align.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s32.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s64.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store_4_unaligned.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store_split_because_of_memsize_or_align.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub_vec.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/test_TypeInfoforMF.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/var_arg.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll<br class=""> llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zext_and_sext.ll<br class=""> llvm/test/CodeGen/Mips/atomic-min-max.ll<br class=""> llvm/test/CodeGen/Mips/atomic.ll<br class=""> llvm/test/CodeGen/Mips/atomic64.ll<br class=""> llvm/test/CodeGen/Mips/atomicCmpSwapPW.ll<br class=""> llvm/test/CodeGen/Mips/copy-fp64.ll<br class=""> llvm/test/CodeGen/Mips/implicit-sret.ll<br class=""> llvm/test/CodeGen/Mips/micromips-eva.mir<br class=""> llvm/test/CodeGen/Mips/msa/ldr_str.ll<br class=""> llvm/test/CodeGen/PowerPC/addegluecrash.ll<br class=""> llvm/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll<br class=""> llvm/test/CodeGen/PowerPC/aix-overflow-toc.py<br class=""> llvm/test/CodeGen/PowerPC/anon_aggr.ll<br class=""> llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll<br class=""> llvm/test/CodeGen/PowerPC/elf-common.ll<br class=""> llvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll<br class=""> llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll<br class=""> llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll<br class=""> llvm/test/CodeGen/PowerPC/fp64-to-int16.ll<br class=""> llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll<br class=""> llvm/test/CodeGen/PowerPC/popcount.ll<br class=""> llvm/test/CodeGen/PowerPC/spill-nor0.ll<br class=""> llvm/test/CodeGen/PowerPC/stack-guard-reassign.ll<br class=""> llvm/test/CodeGen/PowerPC/vsx-args.ll<br class=""> llvm/test/CodeGen/PowerPC/vsx.ll<br class=""> llvm/test/CodeGen/SPARC/fp16-promote.ll<br class=""> llvm/test/CodeGen/SystemZ/swift-return.ll<br class=""> llvm/test/CodeGen/SystemZ/swifterror.ll<br class=""> llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll<br class=""> llvm/test/CodeGen/Thumb2/high-reg-spill.mir<br class=""> llvm/test/CodeGen/Thumb2/mve-vector-spill.ll<br class=""> llvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll<br class=""> llvm/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll<br class=""> llvm/test/CodeGen/X86/2013-10-14-FastISel-incorrect-vreg.ll<br class=""> llvm/test/CodeGen/X86/atomic-monotonic.ll<br class=""> llvm/test/CodeGen/X86/atomic-unordered.ll<br class=""> llvm/test/CodeGen/X86/atomic32.ll<br class=""> llvm/test/CodeGen/X86/atomic64.ll<br class=""> llvm/test/CodeGen/X86/atomic6432.ll<br class=""> llvm/test/CodeGen/X86/avx-load-store.ll<br class=""> llvm/test/CodeGen/X86/avx512-mask-zext-bugfix.ll<br class=""> llvm/test/CodeGen/X86/crash-O0.ll<br class=""> llvm/test/CodeGen/X86/extend-set-cc-uses-dbg.ll<br class=""> llvm/test/CodeGen/X86/fast-isel-cmp-branch.ll<br class=""> llvm/test/CodeGen/X86/fast-isel-nontemporal.ll<br class=""> llvm/test/CodeGen/X86/fast-isel-select-sse.ll<br class=""> llvm/test/CodeGen/X86/fast-isel-select.ll<br class=""> llvm/test/CodeGen/X86/fast-isel-x86-64.ll<br class=""> llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll<br class=""> llvm/test/CodeGen/X86/mixed-ptr-sizes.ll<br class=""> llvm/test/CodeGen/X86/phys-reg-local-regalloc.ll<br class=""> llvm/test/CodeGen/X86/pr11415.ll<br class=""> llvm/test/CodeGen/X86/pr1489.ll<br class=""> llvm/test/CodeGen/X86/pr27591.ll<br class=""> llvm/test/CodeGen/X86/pr30430.ll<br class=""> llvm/test/CodeGen/X86/pr30813.ll<br class=""> llvm/test/CodeGen/X86/pr32241.ll<br class=""> llvm/test/CodeGen/X86/pr32284.ll<br class=""> llvm/test/CodeGen/X86/pr32340.ll<br class=""> llvm/test/CodeGen/X86/pr32345.ll<br class=""> llvm/test/CodeGen/X86/pr32451.ll<br class=""> llvm/test/CodeGen/X86/pr32484.ll<br class=""> llvm/test/CodeGen/X86/pr34592.ll<br class=""> llvm/test/CodeGen/X86/pr34653.ll<br class=""> llvm/test/CodeGen/X86/pr39733.ll<br class=""> llvm/test/CodeGen/X86/pr42452.ll<br class=""> llvm/test/CodeGen/X86/pr44749.ll<br class=""> llvm/test/CodeGen/X86/pr47000.ll<br class=""> llvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir<br class=""> llvm/test/CodeGen/X86/stack-protector-msvc.ll<br class=""> llvm/test/CodeGen/X86/stack-protector-strong-macho-win32-xor.ll<br class=""> llvm/test/CodeGen/X86/swift-return.ll<br class=""> llvm/test/CodeGen/X86/swifterror.ll<br class=""> llvm/test/CodeGen/X86/volatile.ll<br class=""> llvm/test/CodeGen/X86/win64_eh.ll<br class=""> llvm/test/CodeGen/X86/x86-32-intrcc.ll<br class=""> llvm/test/CodeGen/X86/x86-64-intrcc.ll<br class=""> llvm/test/DebugInfo/AArch64/frameindices.ll<br class=""> llvm/test/DebugInfo/AArch64/prologue_end.ll<br class=""> llvm/test/DebugInfo/ARM/prologue_end.ll<br class=""> llvm/test/DebugInfo/Mips/delay-slot.ll<br class=""> llvm/test/DebugInfo/Mips/prologue_end.ll<br class=""> llvm/test/DebugInfo/X86/dbg-declare-arg.ll<br class=""> llvm/test/DebugInfo/X86/fission-ranges.ll<br class=""> llvm/test/DebugInfo/X86/op_deref.ll<br class=""> llvm/test/DebugInfo/X86/parameters.ll<br class=""> llvm/test/DebugInfo/X86/pieces-1.ll<br class=""> llvm/test/DebugInfo/X86/prologue-stack.ll<br class=""> llvm/test/DebugInfo/X86/reference-argument.ll<br class=""> llvm/test/DebugInfo/X86/spill-indirect-nrvo.ll<br class=""> llvm/test/DebugInfo/X86/sret.ll<br class=""> llvm/test/DebugInfo/X86/subreg.ll<br class=""></blockquote></div></div></blockquote></div><br class=""></body></html>