<html><head><meta http-equiv="Content-Type" content="text/html; charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><div class=""><br class=""><div><br class=""><blockquote type="cite" class=""><div class="">On Oct 23, 2020, at 4:14 AM, Qing Shan Zhang <<a href="mailto:qshanz@cn.ibm.com" class="">qshanz@cn.ibm.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><font face="Verdana,Arial,Helvetica,sans-serif" size="2" class="">Hi, Owen,<br class=""><br class="">Could you please open a bug in bugzilla and attach the preprocessed file and the command line options ? It is really hard for me to rebuild the whole project and guess your options ... Thank you.<span class=""><div class=""><br class=""></div>Best regards<br class=""><br class="">steven.zhang(张青山)<br class="">XL/LLVM on Power Compiler Developer<br class=""><br class="">IBM China Development Lab, Shanghai <br class="">Tel: (8621)609-28454 Mobile: +8615900986116<br class="">E-mail: <a href="mailto:qshanz@cn.ibm.com" class="">qshanz@cn.ibm.com</a></span><br class=""><br class=""><font size="2" face="Default Sans Serif,Verdana,Arial,Helvetica,sans-serif" class=""><font color="#990099" class="">-----Owen Anderson <<a href="mailto:resistor@mac.com" target="_blank" class="">resistor@mac.com</a>> wrote: -----</font><div class="iNotesHistory" style="padding-left:5px;"><div style="padding-right:0px;padding-left:5px;border-left:solid black 2px;" class="">To: Qing Shan Zhang <<a href="mailto:qshanz@cn.ibm.com" target="_blank" class="">qshanz@cn.ibm.com</a>><br class="">From: Owen Anderson <<a href="mailto:resistor@mac.com" target="_blank" class="">resistor@mac.com</a>><br class="">Date: 10/23/2020 12:34PM<br class="">Cc: QingShan Zhang <<a href="mailto:llvmlistbot@llvm.org" target="_blank" class="">llvmlistbot@llvm.org</a>>, <a href="mailto:llvm-commits@lists.llvm.org" target="_blank" class="">llvm-commits@lists.llvm.org</a><br class="">Subject: [EXTERNAL] Re: [llvm] ebf3b18 - [Scheduling] Implement a new way to cluster loads/stores<br class=""><br class=""><!-- BaNnErBlUrFlE-HeAdEr-start -->
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Hi Steven,<div class=""><br class=""></div><div class="">The test in question is this source file: <a href="https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_opencv_opencv_blob_master_modules_calib3d_src_dls.cpp&d=DwMFaQ&c=jf_iaSHvJObTbx-siA1ZOg&r=4FedcNQfP4QcaBGfhp8oq2wPQHIv51RNpo7UEhopmZc&m=S_Cc4Lb1D2n-EdPe62FLL2-5I8cZfesL1NprviyMaR0&s=_HGDqYAMSrlO8kOOn_CPZF_l7DOdXGvqf9KMlSMw7Og&e=" class="">https://github.com/opencv/opencv/blob/master/modules/calib3d/src/dls.cpp</a></div><div class=""><br class=""></div><div class="">I haven’t been able to reduce it yet, but I would guess it’s coming from either dls::fill_coeff or dls::cayley_LS_M.</div><div class=""><br class=""></div><div class="">—Owen<br class=""><div class=""><br class=""><blockquote type="cite" class=""><div class="">On Oct 22, 2020, at 7:27 PM, Qing Shan Zhang <<a href="mailto:qshanz@cn.ibm.com" class="">qshanz@cn.ibm.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><font class="" size="2" face="Verdana,Arial,Helvetica,sans-serif">Hi, Owen,<br class=""><br class="">Do you have any test/IR for me so that I can measure the compiling time impact. For now, isReachable() is basing on the dynamic DAG which can be improved to static DAG with the loss of some corner cases.<span class=""> I will have some try to see if it fixes your problem.<br class=""><br class="">Best regards<br class=""><br class="">steven.zhang(张青山)<br class="">XL/LLVM on Power Compiler Developer<br class=""><br class="">IBM China Development Lab, Shanghai <br class="">Tel: (8621)609-28454 Mobile: +8615900986116<br class="">E-mail: <a href="mailto:qshanz@cn.ibm.com" class="">qshanz@cn.ibm.com</a></span><br class=""><br class=""><font class="" size="2" face="Default Sans Serif,Verdana,Arial,Helvetica,sans-serif"><font class="" color="#990099">-----Owen Anderson <<a href="mailto:resistor@mac.com" target="_blank" class="">resistor@mac.com</a>> wrote: -----</font><div class="iNotesHistory" style="padding-left:5px;"><div style="padding-right:0px;padding-left:5px;border-left:solid black 2px;" class="">To: QingShan Zhang <<a href="mailto:qshanz@cn.ibm.com" target="_blank" class="">qshanz@cn.ibm.com</a>>, QingShan Zhang <<a href="mailto:llvmlistbot@llvm.org" target="_blank" class="">llvmlistbot@llvm.org</a>><br class="">From: Owen Anderson <<a href="mailto:resistor@mac.com" target="_blank" class="">resistor@mac.com</a>><br class="">Date: 10/23/2020 02:28AM<br class="">Cc: <a href="mailto:llvm-commits@lists.llvm.org" target="_blank" class="">llvm-commits@lists.llvm.org</a><br class="">Subject: [EXTERNAL] Re: [llvm] ebf3b18 - [Scheduling] Implement a new way to cluster loads/stores<br class=""><br class=""><div class=""><font class="" size="2" face="Courier New,Courier,monospace">Hi QingShan,<br class=""><br class="">I’m seeing significant compile time problems introduced by this change on AArch64, with a worst case example taking >10 minutes to compile. The root cause seems to be the IsReachable() calls introduced here - they’re not cheap, and they’re being called a lot. Is there some way we can back off or limit the number of queries here?<br class=""><br class="">—Owen<br class=""><br class="">> On Aug 26, 2020, at 5:34 AM, QingShan Zhang via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank" class="">llvm-commits@lists.llvm.org</a>> wrote:<br class="">> <br class="">> <br class="">> Author: QingShan Zhang<br class="">> Date: 2020-08-26T12:33:59Z<br class="">> New Revision: ebf3b188c6edcce7e90ddcacbe7c51c90d95b0ac<br class="">> <br class="">> URL: <a href="https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_llvm_llvm-2Dproject_commit_ebf3b188c6edcce7e90ddcacbe7c51c90d95b0ac&d=DwMFaQ&c=jf_iaSHvJObTbx-siA1ZOg&r=4FedcNQfP4QcaBGfhp8oq2wPQHIv51RNpo7UEhopmZc&m=S_Cc4Lb1D2n-EdPe62FLL2-5I8cZfesL1NprviyMaR0&s=RX2b7DcWTP_l-jL5dc4eGFIiwwp-IDVVLaKI0m2rm74&e=" class="">https://github.com/llvm/llvm-project/commit/ebf3b188c6edcce7e90ddcacbe7c51c90d95b0ac</a> <br class="">> DIFF: <a href="https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_llvm_llvm-2Dproject_commit_ebf3b188c6edcce7e90ddcacbe7c51c90d95b0ac.diff&d=DwMFaQ&c=jf_iaSHvJObTbx-siA1ZOg&r=4FedcNQfP4QcaBGfhp8oq2wPQHIv51RNpo7UEhopmZc&m=S_Cc4Lb1D2n-EdPe62FLL2-5I8cZfesL1NprviyMaR0&s=qy8a-h8jwdnffoEGZ-u0PlfEi_mJCLOnA6O8xMdWIXs&e=" class="">https://github.com/llvm/llvm-project/commit/ebf3b188c6edcce7e90ddcacbe7c51c90d95b0ac.diff</a> <br class="">> <br class="">> LOG: [Scheduling] Implement a new way to cluster loads/stores<br class="">> <br class="">> Before calling target hook to determine if two loads/stores are clusterable,<br class="">> we put them into different groups to avoid fake cluster due to dependency.<br class="">> For now, we are putting the loads/stores into the same group if they have<br class="">> the same predecessor. We assume that, if two loads/stores have the same<br class="">> predecessor, it is likely that, they didn't have dependency for each other.<br class="">> <br class="">> However, one SUnit might have several predecessors and for now, we just<br class="">> pick up the first predecessor that has non-data/non-artificial dependency,<br class="">> which is too arbitrary. And we are struggling to fix it.<br class="">> <br class="">> So, I am proposing some better implementation.<br class="">> 1. Collect all the loads/stores that has memory info first to reduce the complexity.<br class="">> 2. Sort these loads/stores so that we can stop the seeking as early as possible.<br class="">> 3. For each load/store, seeking for the first non-dependency instruction with the<br class="">> sorted order, and check if they can cluster or not.<br class="">> <br class="">> Reviewed By: Jay Foad<br class="">> <br class="">> Differential Revision: <a href="https://urldefense.proofpoint.com/v2/url?u=https-3A__reviews.llvm.org_D85517&d=DwMFaQ&c=jf_iaSHvJObTbx-siA1ZOg&r=4FedcNQfP4QcaBGfhp8oq2wPQHIv51RNpo7UEhopmZc&m=S_Cc4Lb1D2n-EdPe62FLL2-5I8cZfesL1NprviyMaR0&s=Gyj_3k8KK3RiZTcbSZ9klcv1-urxz2_MrxXCG1GPz0o&e=" class="">https://reviews.llvm.org/D85517</a> <br class="">> <br class="">> Added: <br class="">> <br class="">> <br class="">> Modified: <br class="">> llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h<br class="">> llvm/lib/CodeGen/MachineScheduler.cpp<br class="">> llvm/test/CodeGen/AArch64/aarch64-stp-cluster.ll<br class="">> llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll<br class="">> llvm/test/CodeGen/AMDGPU/max.i16.ll<br class="">> llvm/test/CodeGen/AMDGPU/stack-realign.ll<br class="">> <br class="">> Removed: <br class="">> <br class="">> <br class="">> <br class="">> ################################################################################<br class="">> diff --git a/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h b/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h<br class="">> index 1eb9b9f322ba..d2b95209d7b4 100644<br class="">> --- a/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h<br class="">> +++ b/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h<br class="">> @@ -268,6 +268,11 @@ namespace llvm {<br class="">> return SU->SchedClass;<br class="">> }<br class="">> <br class="">> + /// IsReachable - Checks if SU is reachable from TargetSU.<br class="">> + bool IsReachable(SUnit *SU, SUnit *TargetSU) {<br class="">> + return Topo.IsReachable(SU, TargetSU);<br class="">> + }<br class="">> +<br class="">> /// Returns an iterator to the top of the current scheduling region.<br class="">> MachineBasicBlock::iterator begin() const { return RegionBegin; }<br class="">> <br class="">> <br class="">> diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp<br class="">> index a8ccf2643f20..b6d0d9a74ac1 100644<br class="">> --- a/llvm/lib/CodeGen/MachineScheduler.cpp<br class="">> +++ b/llvm/lib/CodeGen/MachineScheduler.cpp<br class="">> @@ -1530,7 +1530,10 @@ class BaseMemOpClusterMutation : public ScheduleDAGMutation {<br class="">> void apply(ScheduleDAGInstrs *DAGInstrs) override;<br class="">> <br class="">> protected:<br class="">> - void clusterNeighboringMemOps(ArrayRef<SUnit *> MemOps, ScheduleDAGInstrs *DAG);<br class="">> + void clusterNeighboringMemOps(ArrayRef<MemOpInfo> MemOps,<br class="">> + ScheduleDAGInstrs *DAG);<br class="">> + void collectMemOpRecords(std::vector<SUnit> &SUnits,<br class="">> + SmallVectorImpl<MemOpInfo> &MemOpRecords);<br class="">> };<br class="">> <br class="">> class StoreClusterMutation : public BaseMemOpClusterMutation {<br class="">> @@ -1566,63 +1569,53 @@ createStoreClusterDAGMutation(const TargetInstrInfo *TII,<br class="">> <br class="">> } // end namespace llvm<br class="">> <br class="">> +// Sorting all the loads/stores first, then for each load/store, checking the<br class="">> +// following load/store one by one, until reach the first non-dependent one and<br class="">> +// call target hook to see if they can cluster.<br class="">> void BaseMemOpClusterMutation::clusterNeighboringMemOps(<br class="">> - ArrayRef<SUnit *> MemOps, ScheduleDAGInstrs *DAG) {<br class="">> - SmallVector<MemOpInfo, 32> MemOpRecords;<br class="">> - for (SUnit *SU : MemOps) {<br class="">> - const MachineInstr &MI = *SU->getInstr();<br class="">> - SmallVector<const MachineOperand *, 4> BaseOps;<br class="">> - int64_t Offset;<br class="">> - bool OffsetIsScalable;<br class="">> - unsigned Width;<br class="">> - if (TII->getMemOperandsWithOffsetWidth(MI, BaseOps, Offset,<br class="">> - OffsetIsScalable, Width, TRI)) {<br class="">> - MemOpRecords.push_back(MemOpInfo(SU, BaseOps, Offset, Width));<br class="">> -<br class="">> - LLVM_DEBUG(dbgs() << "Num BaseOps: " << BaseOps.size() << ", Offset: "<br class="">> - << Offset << ", OffsetIsScalable: " << OffsetIsScalable<br class="">> - << ", Width: " << Width << "\n");<br class="">> - }<br class="">> -#ifndef NDEBUG<br class="">> - for (auto *Op : BaseOps)<br class="">> - assert(Op);<br class="">> -#endif<br class="">> - }<br class="">> - if (MemOpRecords.size() < 2)<br class="">> - return;<br class="">> -<br class="">> - llvm::sort(MemOpRecords);<br class="">> + ArrayRef<MemOpInfo> MemOpRecords, ScheduleDAGInstrs *DAG) {<br class="">> + // Keep track of the current cluster length and bytes for each SUnit.<br class="">> + DenseMap<unsigned, std::pair<unsigned, unsigned>> SUnit2ClusterInfo;<br class="">> <br class="">> // At this point, `MemOpRecords` array must hold atleast two mem ops. Try to<br class="">> // cluster mem ops collected within `MemOpRecords` array.<br class="">> - unsigned ClusterLength = 1;<br class="">> - unsigned CurrentClusterBytes = MemOpRecords[0].Width;<br class="">> for (unsigned Idx = 0, End = MemOpRecords.size(); Idx < (End - 1); ++Idx) {<br class="">> // Decision to cluster mem ops is taken based on target dependent logic<br class="">> auto MemOpa = MemOpRecords[Idx];<br class="">> - auto MemOpb = MemOpRecords[Idx + 1];<br class="">> - ++ClusterLength;<br class="">> - CurrentClusterBytes += MemOpb.Width;<br class="">> - if (!TII->shouldClusterMemOps(MemOpa.BaseOps, MemOpb.BaseOps, ClusterLength,<br class="">> - CurrentClusterBytes)) {<br class="">> - // Current mem ops pair could not be clustered, reset cluster length, and<br class="">> - // go to next pair<br class="">> - ClusterLength = 1;<br class="">> - CurrentClusterBytes = MemOpb.Width;<br class="">> +<br class="">> + // Seek for the next load/store to do the cluster.<br class="">> + unsigned NextIdx = Idx + 1;<br class="">> + for (; NextIdx < End; ++NextIdx)<br class="">> + // Skip if MemOpb has been clustered already or has dependency with<br class="">> + // MemOpa.<br class="">> + if (!SUnit2ClusterInfo.count(MemOpRecords[NextIdx].SU->NodeNum) &&<br class="">> + !DAG->IsReachable(MemOpRecords[NextIdx].SU, MemOpa.SU) &&<br class="">> + !DAG->IsReachable(MemOpa.SU, MemOpRecords[NextIdx].SU))<br class="">> + break;<br class="">> + if (NextIdx == End)<br class="">> continue;<br class="">> +<br class="">> + auto MemOpb = MemOpRecords[NextIdx];<br class="">> + unsigned ClusterLength = 2;<br class="">> + unsigned CurrentClusterBytes = MemOpa.Width + MemOpb.Width;<br class="">> + if (SUnit2ClusterInfo.count(MemOpa.SU->NodeNum)) {<br class="">> + ClusterLength = SUnit2ClusterInfo[MemOpa.SU->NodeNum].first + 1;<br class="">> + CurrentClusterBytes =<br class="">> + SUnit2ClusterInfo[MemOpa.SU->NodeNum].second + MemOpb.Width;<br class="">> }<br class="">> <br class="">> + if (!TII->shouldClusterMemOps(MemOpa.BaseOps, MemOpb.BaseOps, ClusterLength,<br class="">> + CurrentClusterBytes))<br class="">> + continue;<br class="">> +<br class="">> SUnit *SUa = MemOpa.SU;<br class="">> SUnit *SUb = MemOpb.SU;<br class="">> if (SUa->NodeNum > SUb->NodeNum)<br class="">> std::swap(SUa, SUb);<br class="">> <br class="">> // FIXME: Is this check really required?<br class="">> - if (!DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {<br class="">> - ClusterLength = 1;<br class="">> - CurrentClusterBytes = MemOpb.Width;<br class="">> + if (!DAG->addEdge(SUb, SDep(SUa, SDep::Cluster)))<br class="">> continue;<br class="">> - }<br class="">> <br class="">> LLVM_DEBUG(dbgs() << "Cluster ld/st SU(" << SUa->NodeNum << ") - SU("<br class="">> << SUb->NodeNum << ")\n");<br class="">> @@ -1656,42 +1649,57 @@ void BaseMemOpClusterMutation::clusterNeighboringMemOps(<br class="">> }<br class="">> }<br class="">> <br class="">> + SUnit2ClusterInfo[MemOpb.SU->NodeNum] = {ClusterLength,<br class="">> + CurrentClusterBytes};<br class="">> +<br class="">> LLVM_DEBUG(dbgs() << " Curr cluster length: " << ClusterLength<br class="">> << ", Curr cluster bytes: " << CurrentClusterBytes<br class="">> << "\n");<br class="">> }<br class="">> }<br class="">> <br class="">> -/// Callback from DAG postProcessing to create cluster edges for loads.<br class="">> -void BaseMemOpClusterMutation::apply(ScheduleDAGInstrs *DAG) {<br class="">> - // Map DAG NodeNum to a set of dependent MemOps in store chain.<br class="">> - DenseMap<unsigned, SmallVector<SUnit *, 4>> StoreChains;<br class="">> - for (SUnit &SU : DAG->SUnits) {<br class="">> +void BaseMemOpClusterMutation::collectMemOpRecords(<br class="">> + std::vector<SUnit> &SUnits, SmallVectorImpl<MemOpInfo> &MemOpRecords) {<br class="">> + for (auto &SU : SUnits) {<br class="">> if ((IsLoad && !SU.getInstr()->mayLoad()) ||<br class="">> (!IsLoad && !SU.getInstr()->mayStore()))<br class="">> continue;<br class="">> <br class="">> - unsigned ChainPredID = DAG->SUnits.size();<br class="">> - for (const SDep &Pred : SU.Preds) {<br class="">> - // We only want to cluster the mem ops that have the same ctrl(non-data)<br class="">> - // pred so that they didn't have ctrl dependency for each other. But for<br class="">> - // store instrs, we can still cluster them if the pred is load instr.<br class="">> - if ((Pred.isCtrl() &&<br class="">> - (IsLoad ||<br class="">> - (Pred.getSUnit() && Pred.getSUnit()->getInstr()->mayStore()))) &&<br class="">> - !Pred.isArtificial()) {<br class="">> - ChainPredID = Pred.getSUnit()->NodeNum;<br class="">> - break;<br class="">> - }<br class="">> + const MachineInstr &MI = *SU.getInstr();<br class="">> + SmallVector<const MachineOperand *, 4> BaseOps;<br class="">> + int64_t Offset;<br class="">> + bool OffsetIsScalable;<br class="">> + unsigned Width;<br class="">> + if (TII->getMemOperandsWithOffsetWidth(MI, BaseOps, Offset,<br class="">> + OffsetIsScalable, Width, TRI)) {<br class="">> + MemOpRecords.push_back(MemOpInfo(&SU, BaseOps, Offset, Width));<br class="">> +<br class="">> + LLVM_DEBUG(dbgs() << "Num BaseOps: " << BaseOps.size() << ", Offset: "<br class="">> + << Offset << ", OffsetIsScalable: " << OffsetIsScalable<br class="">> + << ", Width: " << Width << "\n");<br class="">> }<br class="">> - // Insert the SU to corresponding store chain.<br class="">> - auto &Chain = StoreChains.FindAndConstruct(ChainPredID).second;<br class="">> - Chain.push_back(&SU);<br class="">> +#ifndef NDEBUG<br class="">> + for (auto *Op : BaseOps)<br class="">> + assert(Op);<br class="">> +#endif<br class="">> }<br class="">> +}<br class="">> +<br class="">> +/// Callback from DAG postProcessing to create cluster edges for loads/stores.<br class="">> +void BaseMemOpClusterMutation::apply(ScheduleDAGInstrs *DAG) {<br class="">> + // Collect all the clusterable loads/stores<br class="">> + SmallVector<MemOpInfo, 32> MemOpRecords;<br class="">> + collectMemOpRecords(DAG->SUnits, MemOpRecords);<br class="">> +<br class="">> + if (MemOpRecords.size() < 2)<br class="">> + return;<br class="">> +<br class="">> + // Sorting the loads/stores, so that, we can stop the cluster as early as<br class="">> + // possible.<br class="">> + llvm::sort(MemOpRecords);<br class="">> <br class="">> - // Iterate over the store chains.<br class="">> - for (auto &SCD : StoreChains)<br class="">> - clusterNeighboringMemOps(SCD.second, DAG);<br class="">> + // Trying to cluster all the neighboring loads/stores.<br class="">> + clusterNeighboringMemOps(MemOpRecords, DAG);<br class="">> }<br class="">> <br class="">> //===----------------------------------------------------------------------===//<br class="">> <br class="">> diff --git a/llvm/test/CodeGen/AArch64/aarch64-stp-cluster.ll b/llvm/test/CodeGen/AArch64/aarch64-stp-cluster.ll<br class="">> index b0ed3d0490cc..e95321582def 100644<br class="">> --- a/llvm/test/CodeGen/AArch64/aarch64-stp-cluster.ll<br class="">> +++ b/llvm/test/CodeGen/AArch64/aarch64-stp-cluster.ll<br class="">> @@ -214,11 +214,11 @@ entry:<br class="">> ret void<br class="">> }<br class="">> <br class="">> -; FIXME - The SU(4) and SU(7) can be clustered even with<br class="">> +; Verify that the SU(4) and SU(7) can be clustered even with<br class="">> ; <br class="">> diff erent preds<br class="">> ; CHECK: ********** MI Scheduling **********<br class="">> ; CHECK-LABEL: cluster_with_<br class="">> diff erent_preds:%bb.0<br class="">> -; CHECK-NOT:Cluster ld/st SU(4) - SU(7)<br class="">> +; CHECK:Cluster ld/st SU(4) - SU(7)<br class="">> ; CHECK:SU(3): STRWui %2:gpr32, %0:gpr64common, 0 ::<br class="">> ; CHECK:SU(4): %3:gpr32 = LDRWui %1:gpr64common, 0 ::<br class="">> ; CHECK:Predecessors:<br class="">> <br class="">> diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll<br class="">> index 2dc47ca94aa9..d23538cadcbd 100644<br class="">> --- a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll<br class="">> +++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll<br class="">> @@ -624,9 +624,9 @@ define void @too_many_args_use_workitem_id_x_byval(<br class="">> <br class="">> <br class="">> ; FIXEDABI: v_mov_b32_e32 [[K0:v[0-9]+]], 0x3e7<br class="">> +; FIXEDABI: buffer_store_dword [[K0]], off, s[0:3], 0 offset:4{{$}}<br class="">> ; FIXEDABI: s_movk_i32 s32, 0x400{{$}}<br class="">> ; FIXEDABI: v_mov_b32_e32 [[K1:v[0-9]+]], 0x140<br class="">> -; FIXEDABI: buffer_store_dword [[K0]], off, s[0:3], 0 offset:4{{$}}<br class="">> <br class="">> ; FIXEDABI: buffer_store_dword [[K1]], off, s[0:3], s32{{$}}<br class="">> <br class="">> @@ -669,8 +669,8 @@ define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_byval() #1<br class="">> <br class="">> ; FIXED-ABI-NOT: v31<br class="">> ; FIXEDABI: v_mov_b32_e32 [[K0:v[0-9]+]], 0x3e7{{$}}<br class="">> -; FIXEDABI: v_mov_b32_e32 [[K1:v[0-9]+]], 0x140{{$}}<br class="">> ; FIXEDABI: buffer_store_dword [[K0]], off, s[0:3], s33{{$}}<br class="">> +; FIXEDABI: v_mov_b32_e32 [[K1:v[0-9]+]], 0x140{{$}}<br class="">> ; FIXEDABI: buffer_store_dword [[K1]], off, s[0:3], s32{{$}}<br class="">> ; FIXEDABI: buffer_load_dword [[RELOAD_BYVAL:v[0-9]+]], off, s[0:3], s33{{$}}<br class="">> <br class="">> <br class="">> diff --git a/llvm/test/CodeGen/AMDGPU/max.i16.ll b/llvm/test/CodeGen/AMDGPU/max.i16.ll<br class="">> index c64e400e628f..7c4ce5d6c1ff 100644<br class="">> --- a/llvm/test/CodeGen/AMDGPU/max.i16.ll<br class="">> +++ b/llvm/test/CodeGen/AMDGPU/max.i16.ll<br class="">> @@ -145,14 +145,14 @@ define amdgpu_kernel void @v_test_imax_sge_v3i16(<3 x i16> addrspace(1)* %out, <<br class="">> ; GFX9-NEXT: v_mov_b32_e32 v1, 0<br class="">> ; GFX9-NEXT: v_mov_b32_e32 v2, 0<br class="">> ; GFX9-NEXT: s_waitcnt lgkmcnt(0)<br class="">> -; GFX9-NEXT: global_load_short_d16 v2, v0, s[6:7] offset:4<br class="">> ; GFX9-NEXT: global_load_short_d16 v1, v0, s[0:1] offset:4<br class="">> -; GFX9-NEXT: global_load_dword v3, v0, s[6:7]<br class="">> -; GFX9-NEXT: global_load_dword v4, v0, s[0:1]<br class="">> -; GFX9-NEXT: s_waitcnt vmcnt(2)<br class="">> +; GFX9-NEXT: global_load_dword v3, v0, s[0:1]<br class="">> +; GFX9-NEXT: global_load_short_d16 v2, v0, s[6:7] offset:4<br class="">> +; GFX9-NEXT: global_load_dword v4, v0, s[6:7]<br class="">> +; GFX9-NEXT: s_waitcnt vmcnt(1)<br class="">> ; GFX9-NEXT: v_pk_max_i16 v1, v2, v1<br class="">> ; GFX9-NEXT: s_waitcnt vmcnt(0)<br class="">> -; GFX9-NEXT: v_pk_max_i16 v3, v3, v4<br class="">> +; GFX9-NEXT: v_pk_max_i16 v3, v4, v3<br class="">> ; GFX9-NEXT: global_store_short v0, v1, s[4:5] offset:4<br class="">> ; GFX9-NEXT: global_store_dword v0, v3, s[4:5]<br class="">> ; GFX9-NEXT: s_endpgm<br class="">> <br class="">> diff --git a/llvm/test/CodeGen/AMDGPU/stack-realign.ll b/llvm/test/CodeGen/AMDGPU/stack-realign.ll<br class="">> index 74b53802ef5b..e8e3518aed1c 100644<br class="">> --- a/llvm/test/CodeGen/AMDGPU/stack-realign.ll<br class="">> +++ b/llvm/test/CodeGen/AMDGPU/stack-realign.ll<br class="">> @@ -160,16 +160,14 @@ define void @func_call_align1024_bp_gets_vgpr_spill(<32 x i32> %a, i32 %b) #0 {<br class="">> ; GCN-NEXT: s_mov_b64 exec, s[4:5]<br class="">> ; GCN-NEXT: v_writelane_b32 [[VGPR_REG]], s33, 2<br class="">> ; GCN-NEXT: v_writelane_b32 [[VGPR_REG]], s34, 3<br class="">> -; GCN: s_mov_b32 s34, s32<br class="">> ; GCN: s_add_u32 [[SCRATCH_REG:s[0-9]+]], s32, 0xffc0<br class="">> ; GCN: s_and_b32 s33, [[SCRATCH_REG]], 0xffff0000<br class="">> +; GCN: s_mov_b32 s34, s32<br class="">> +; GCN: v_mov_b32_e32 v32, 0<br class="">> +; GCN: buffer_store_dword v32, off, s[0:3], s33 offset:1024<br class="">> ; GCN-NEXT: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s34<br class="">> ; GCN-NEXT: s_add_u32 s32, s32, 0x30000<br class="">> <br class="">> -; GCN: v_mov_b32_e32 v33, 0<br class="">> -<br class="">> -; GCN: buffer_store_dword v33, off, s[0:3], s33 offset:1024<br class="">> -<br class="">> ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s32<br class="">> ; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]<br class="">> <br class="">> <br class="">> <br class="">> <br class="">> _______________________________________________<br class="">> llvm-commits mailing list<br class="">> <a href="mailto:llvm-commits@lists.llvm.org" target="_blank" class="">llvm-commits@lists.llvm.org</a><br class="">> <a href="https://urldefense.proofpoint.com/v2/url?u=https-3A__lists.llvm.org_cgi-2Dbin_mailman_listinfo_llvm-2Dcommits&d=DwMFaQ&c=jf_iaSHvJObTbx-siA1ZOg&r=4FedcNQfP4QcaBGfhp8oq2wPQHIv51RNpo7UEhopmZc&m=S_Cc4Lb1D2n-EdPe62FLL2-5I8cZfesL1NprviyMaR0&s=X_pWCy6LUnCpN-gcnihGybJiQvSN7R2SA-yxNNJM1w4&e=" class="">https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a> <br class=""><br class=""></font></div></div></div></font></font><br class=""></div></blockquote></div><br class=""></div></div></div></font></font><br class="">
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