<div dir="ltr"><div>Hello Matt,</div><div><br></div><div>It looks like this commit is causing machine code verification errors on green dragon. Can you please take a look? <a href="http://lab.llvm.org:8080/green/job/test-suite-verify-machineinstrs-aarch64-globalisel-O0-g/8092/">http://lab.llvm.org:8080/green/job/test-suite-verify-machineinstrs-aarch64-globalisel-O0-g/8092/</a><br></div><div><br></div><div>Thanks,</div><div>Erik<br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, Aug 4, 2020 at 4:56 PM Matt Arsenault via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
Author: Matt Arsenault<br>
Date: 2020-08-04T16:55:55-04:00<br>
New Revision: f8fb7835d6a5e2a75d412e1482fc1c039efef1f0<br>
<br>
URL: <a href="https://github.com/llvm/llvm-project/commit/f8fb7835d6a5e2a75d412e1482fc1c039efef1f0" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/f8fb7835d6a5e2a75d412e1482fc1c039efef1f0</a><br>
DIFF: <a href="https://github.com/llvm/llvm-project/commit/f8fb7835d6a5e2a75d412e1482fc1c039efef1f0.diff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/f8fb7835d6a5e2a75d412e1482fc1c039efef1f0.diff</a><br>
<br>
LOG: GlobalISel: Add utilty for getting function argument live ins<br>
<br>
Get the argument register and ensure there's a copy to the virtual<br>
register. AMDGPU and AArch64 have similarish code to get the livein<br>
value, and I also want to use this in multiple places.<br>
<br>
This is a bit more aggressive about setting the register class than<br>
the original function, but that's probably OK.<br>
<br>
I think we're missing a few verifier checks for function live ins. I<br>
noticed AArch64's calling convention code is not actually adding<br>
liveins to functions, only the entry block (which apparently might not<br>
matter that much?). There should probably be a verifier check that<br>
entry block live ins are also live into the function. We also might<br>
need a verifier check that the copy to the livein virtual register is<br>
in the entry block.<br>
<br>
Added: <br>
<br>
<br>
Modified: <br>
llvm/include/llvm/CodeGen/GlobalISel/Utils.h<br>
llvm/lib/CodeGen/GlobalISel/Utils.cpp<br>
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp<br>
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp<br>
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h<br>
llvm/test/CodeGen/AArch64/GlobalISel/select-returnaddress-liveins.mir<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll<br>
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir<br>
<br>
Removed: <br>
<br>
<br>
<br>
################################################################################<br>
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h<br>
index 35add316b5b6..a44e936ef5d6 100644<br>
--- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h<br>
+++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h<br>
@@ -190,6 +190,17 @@ inline bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI) {<br>
<br>
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO);<br>
<br>
+/// Return a virtual register corresponding to the incoming argument register \p<br>
+/// PhysReg. This register is expected to have class \p RC, and optional type \p<br>
+/// RegTy. This assumes all references to the register will use the same type.<br>
+///<br>
+/// If there is an existing live-in argument register, it will be returned.<br>
+/// This will also ensure there is a valid copy<br>
+Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII,<br>
+ MCRegister PhysReg,<br>
+ const TargetRegisterClass &RC,<br>
+ LLT RegTy = LLT());<br>
+<br>
/// Return the least common multiple type of \p OrigTy and \p TargetTy, by changing the<br>
/// number of vector elements or scalar bitwidth. The intent is a<br>
/// G_MERGE_VALUES, G_BUILD_VECTOR, or G_CONCAT_VECTORS can be constructed from<br>
<br>
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp<br>
index 7fc738adb339..b59064ecf868 100644<br>
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp<br>
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp<br>
@@ -497,6 +497,40 @@ Align llvm::inferAlignFromPtrInfo(MachineFunction &MF,<br>
return Align(1);<br>
}<br>
<br>
+Register llvm::getFunctionLiveInPhysReg(MachineFunction &MF,<br>
+ const TargetInstrInfo &TII,<br>
+ MCRegister PhysReg,<br>
+ const TargetRegisterClass &RC,<br>
+ LLT RegTy) {<br>
+ DebugLoc DL; // FIXME: Is no location the right choice?<br>
+ MachineBasicBlock &EntryMBB = MF.front();<br>
+ MachineRegisterInfo &MRI = MF.getRegInfo();<br>
+ Register LiveIn = MRI.getLiveInVirtReg(PhysReg);<br>
+ if (LiveIn) {<br>
+ MachineInstr *Def = MRI.getVRegDef(LiveIn);<br>
+ if (Def) {<br>
+ // FIXME: Should the verifier check this is in the entry block?<br>
+ assert(Def->getParent() == &EntryMBB && "live-in copy not in entry block");<br>
+ return LiveIn;<br>
+ }<br>
+<br>
+ // It's possible the incoming argument register and copy was added during<br>
+ // lowering, but later deleted due to being/becoming dead. If this happens,<br>
+ // re-insert the copy.<br>
+ } else {<br>
+ // The live in register was not present, so add it.<br>
+ LiveIn = MF.addLiveIn(PhysReg, &RC);<br>
+ if (RegTy.isValid())<br>
+ MRI.setType(LiveIn, RegTy);<br>
+ }<br>
+<br>
+ BuildMI(EntryMBB, EntryMBB.begin(), DL, TII.get(TargetOpcode::COPY), LiveIn)<br>
+ .addReg(PhysReg);<br>
+ if (!EntryMBB.isLiveIn(PhysReg))<br>
+ EntryMBB.addLiveIn(PhysReg);<br>
+ return LiveIn;<br>
+}<br>
+<br>
Optional<APInt> llvm::ConstantFoldExtOp(unsigned Opcode, const Register Op1,<br>
uint64_t Imm,<br>
const MachineRegisterInfo &MRI) {<br>
<br>
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp<br>
index 9f7950851f65..8721a535154a 100644<br>
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp<br>
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp<br>
@@ -4784,16 +4784,15 @@ bool AArch64InstructionSelector::selectIntrinsic(MachineInstr &I,<br>
I.eraseFromParent();<br>
return true;<br>
}<br>
+<br>
MFI.setReturnAddressIsTaken(true);<br>
- MF.addLiveIn(AArch64::LR, &AArch64::GPR64spRegClass);<br>
+<br>
// Insert the copy from LR/X30 into the entry block, before it can be<br>
// clobbered by anything.<br>
- MachineBasicBlock &EntryBlock = *MF.begin();<br>
- if (!EntryBlock.isLiveIn(AArch64::LR))<br>
- EntryBlock.addLiveIn(AArch64::LR);<br>
- MachineIRBuilder EntryBuilder(MF);<br>
- EntryBuilder.setInstr(*EntryBlock.begin());<br>
- EntryBuilder.buildCopy({DstReg}, {Register(AArch64::LR)});<br>
+ Register LiveInLR = getFunctionLiveInPhysReg(MF, TII, AArch64::LR,<br>
+ AArch64::GPR64spRegClass);<br>
+ MIRBuilder.buildCopy(DstReg, LiveInLR);<br>
+<br>
MFReturnAddr = DstReg;<br>
I.eraseFromParent();<br>
return true;<br>
<br>
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp<br>
index b40870024cc4..33992cacddb7 100644<br>
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp<br>
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp<br>
@@ -2494,53 +2494,6 @@ static MachineInstr *verifyCFIntrinsic(MachineInstr &MI,<br>
return &UseMI;<br>
}<br>
<br>
-Register AMDGPULegalizerInfo::insertLiveInCopy(MachineIRBuilder &B,<br>
- MachineRegisterInfo &MRI,<br>
- Register LiveIn,<br>
- Register PhyReg) const {<br>
- assert(PhyReg.isPhysical() && "Physical register expected");<br>
-<br>
- // Insert the live-in copy, if required, by defining destination virtual<br>
- // register.<br>
- // FIXME: It seems EmitLiveInCopies isn't called anywhere?<br>
- if (!MRI.getVRegDef(LiveIn)) {<br>
- // FIXME: Should have scoped insert pt<br>
- MachineBasicBlock &OrigInsBB = B.getMBB();<br>
- auto OrigInsPt = B.getInsertPt();<br>
-<br>
- MachineBasicBlock &EntryMBB = B.getMF().front();<br>
- EntryMBB.addLiveIn(PhyReg);<br>
- B.setInsertPt(EntryMBB, EntryMBB.begin());<br>
- B.buildCopy(LiveIn, PhyReg);<br>
-<br>
- B.setInsertPt(OrigInsBB, OrigInsPt);<br>
- }<br>
-<br>
- return LiveIn;<br>
-}<br>
-<br>
-Register AMDGPULegalizerInfo::getLiveInRegister(MachineIRBuilder &B,<br>
- MachineRegisterInfo &MRI,<br>
- Register PhyReg, LLT Ty,<br>
- bool InsertLiveInCopy) const {<br>
- assert(PhyReg.isPhysical() && "Physical register expected");<br>
-<br>
- // Get or create virtual live-in regester<br>
- Register LiveIn = MRI.getLiveInVirtReg(PhyReg);<br>
- if (!LiveIn) {<br>
- LiveIn = MRI.createGenericVirtualRegister(Ty);<br>
- MRI.addLiveIn(PhyReg, LiveIn);<br>
- }<br>
-<br>
- // When the actual true copy required is from virtual register to physical<br>
- // register (to be inserted later), live-in copy insertion from physical<br>
- // to register virtual register is not required<br>
- if (!InsertLiveInCopy)<br>
- return LiveIn;<br>
-<br>
- return insertLiveInCopy(B, MRI, LiveIn, PhyReg);<br>
-}<br>
-<br>
bool AMDGPULegalizerInfo::loadInputValue(Register DstReg, MachineIRBuilder &B,<br>
const ArgDescriptor *Arg,<br>
const TargetRegisterClass *ArgRC,<br>
@@ -2549,9 +2502,8 @@ bool AMDGPULegalizerInfo::loadInputValue(Register DstReg, MachineIRBuilder &B,<br>
assert(SrcReg.isPhysical() && "Physical register expected");<br>
assert(DstReg.isVirtual() && "Virtual register expected");<br>
<br>
- MachineRegisterInfo &MRI = *B.getMRI();<br>
- Register LiveIn = getLiveInRegister(B, MRI, SrcReg, ArgTy);<br>
-<br>
+ Register LiveIn = getFunctionLiveInPhysReg(B.getMF(), B.getTII(), SrcReg, *ArgRC,<br>
+ ArgTy);<br>
if (Arg->isMasked()) {<br>
// TODO: Should we try to emit this once in the entry block?<br>
const LLT S32 = LLT::scalar(32);<br>
@@ -4195,6 +4147,7 @@ bool AMDGPULegalizerInfo::legalizeSBufferLoad(<br>
return true;<br>
}<br>
<br>
+// TODO: Move to selection<br>
bool AMDGPULegalizerInfo::legalizeTrapIntrinsic(MachineInstr &MI,<br>
MachineRegisterInfo &MRI,<br>
MachineIRBuilder &B) const {<br>
@@ -4206,12 +4159,13 @@ bool AMDGPULegalizerInfo::legalizeTrapIntrinsic(MachineInstr &MI,<br>
// Pass queue pointer to trap handler as input, and insert trap instruction<br>
// Reference: <a href="https://llvm.org/docs/AMDGPUUsage.html#trap-handler-abi" rel="noreferrer" target="_blank">https://llvm.org/docs/AMDGPUUsage.html#trap-handler-abi</a><br>
MachineRegisterInfo &MRI = *B.getMRI();<br>
- Register SGPR01(AMDGPU::SGPR0_SGPR1);<br>
- Register LiveIn = getLiveInRegister(<br>
- B, MRI, SGPR01, LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64),<br>
- /*InsertLiveInCopy=*/false);<br>
+<br>
+ Register LiveIn =<br>
+ MRI.createGenericVirtualRegister(LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));<br>
if (!loadInputValue(LiveIn, B, AMDGPUFunctionArgInfo::QUEUE_PTR))<br>
return false;<br>
+<br>
+ Register SGPR01(AMDGPU::SGPR0_SGPR1);<br>
B.buildCopy(SGPR01, LiveIn);<br>
B.buildInstr(AMDGPU::S_TRAP)<br>
.addImm(GCNSubtarget::TrapIDLLVMTrap)<br>
<br>
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h<br>
index 332d675c1a88..99191487f90d 100644<br>
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h<br>
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h<br>
@@ -86,11 +86,6 @@ class AMDGPULegalizerInfo final : public LegalizerInfo {<br>
bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI,<br>
MachineIRBuilder &B) const;<br>
<br>
- Register getLiveInRegister(MachineIRBuilder &B, MachineRegisterInfo &MRI,<br>
- Register PhyReg, LLT Ty,<br>
- bool InsertLiveInCopy = true) const;<br>
- Register insertLiveInCopy(MachineIRBuilder &B, MachineRegisterInfo &MRI,<br>
- Register LiveIn, Register PhyReg) const;<br>
bool loadInputValue(Register DstReg, MachineIRBuilder &B,<br>
const ArgDescriptor *Arg,<br>
const TargetRegisterClass *ArgRC, LLT ArgTy) const;<br>
<br>
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-returnaddress-liveins.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-returnaddress-liveins.mir<br>
index 433c7848433f..745752dcc342 100644<br>
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-returnaddress-liveins.mir<br>
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-returnaddress-liveins.mir<br>
@@ -17,10 +17,11 @@ body: |<br>
; CHECK: bb.0:<br>
; CHECK: successors: %bb.1(0x80000000)<br>
; CHECK: liveins: $w0, $x0, $lr<br>
- ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $lr<br>
+ ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $lr<br>
; CHECK: B %bb.1<br>
; CHECK: bb.1:<br>
- ; CHECK: $x0 = COPY [[COPY]]<br>
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]<br>
+ ; CHECK: $x0 = COPY [[COPY1]]<br>
; CHECK: RET_ReallyLR implicit $x0<br>
; LR should be added as a livein to the entry block.<br>
<br>
@@ -44,10 +45,11 @@ body: |<br>
; CHECK: bb.0:<br>
; CHECK: successors: %bb.1(0x80000000)<br>
; CHECK: liveins: $w0, $x0, $lr<br>
- ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $lr<br>
+ ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $lr<br>
; CHECK: B %bb.1<br>
; CHECK: bb.1:<br>
- ; CHECK: $x0 = COPY [[COPY]]<br>
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]<br>
+ ; CHECK: $x0 = COPY [[COPY1]]<br>
; CHECK: RET_ReallyLR implicit $x0<br>
; We should not have LR listed as a livein twice.<br>
<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll<br>
index aa0850a5dbe5..0cb51aef3fa1 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll<br>
@@ -115,7 +115,7 @@ define void @test_func_call_external_void_func_i32() #0 {<br>
; GFX900-LABEL: name: test_func_call_external_void_func_i32<br>
; GFX900: bb.1 (%ir-block.0):<br>
; GFX900: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31<br>
- ; GFX900: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr31<br>
+ ; GFX900: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31<br>
; GFX900: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr14<br>
; GFX900: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr13<br>
; GFX900: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr12<br>
@@ -153,7 +153,7 @@ define void @test_func_call_external_void_func_i32() #0 {<br>
; GFX908-LABEL: name: test_func_call_external_void_func_i32<br>
; GFX908: bb.1 (%ir-block.0):<br>
; GFX908: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31<br>
- ; GFX908: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr31<br>
+ ; GFX908: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31<br>
; GFX908: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr14<br>
; GFX908: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr13<br>
; GFX908: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr12<br>
@@ -373,7 +373,7 @@ define void @test_func_call_external_void_func_v32i32([17 x i8]) #0 {<br>
; GFX900-LABEL: name: test_func_call_external_void_func_v32i32<br>
; GFX900: bb.1 (%ir-block.1):<br>
; GFX900: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31<br>
- ; GFX900: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr31<br>
+ ; GFX900: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31<br>
; GFX900: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr14<br>
; GFX900: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr13<br>
; GFX900: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr12<br>
@@ -498,7 +498,7 @@ define void @test_func_call_external_void_func_v32i32([17 x i8]) #0 {<br>
; GFX908-LABEL: name: test_func_call_external_void_func_v32i32<br>
; GFX908: bb.1 (%ir-block.1):<br>
; GFX908: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31<br>
- ; GFX908: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr31<br>
+ ; GFX908: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31<br>
; GFX908: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr14<br>
; GFX908: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr13<br>
; GFX908: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr12<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll<br>
index 6b29697ca086..b3a8aac96df9 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll<br>
@@ -142,7 +142,7 @@ define void @test_func_call_external_void_func_void() #0 {<br>
; CHECK-LABEL: name: test_func_call_external_void_func_void<br>
; CHECK: bb.1 (%ir-block.0):<br>
; CHECK: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31<br>
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr31<br>
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31<br>
; CHECK: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr14<br>
; CHECK: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr13<br>
; CHECK: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr12<br>
@@ -4369,7 +4369,7 @@ define void @stack_12xv3i32() #0 {<br>
; CHECK-LABEL: name: stack_12xv3i32<br>
; CHECK: bb.1.entry:<br>
; CHECK: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31<br>
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr31<br>
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31<br>
; CHECK: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr14<br>
; CHECK: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr13<br>
; CHECK: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr12<br>
@@ -4510,7 +4510,7 @@ define void @stack_12xv3f32() #0 {<br>
; CHECK-LABEL: name: stack_12xv3f32<br>
; CHECK: bb.1.entry:<br>
; CHECK: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31<br>
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr31<br>
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31<br>
; CHECK: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr14<br>
; CHECK: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr13<br>
; CHECK: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr12<br>
@@ -4651,7 +4651,7 @@ define void @stack_8xv5i32() #0 {<br>
; CHECK-LABEL: name: stack_8xv5i32<br>
; CHECK: bb.1.entry:<br>
; CHECK: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31<br>
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr31<br>
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31<br>
; CHECK: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr14<br>
; CHECK: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr13<br>
; CHECK: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr12<br>
@@ -4792,7 +4792,7 @@ define void @stack_8xv5f32() #0 {<br>
; CHECK-LABEL: name: stack_8xv5f32<br>
; CHECK: bb.1.entry:<br>
; CHECK: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31<br>
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr31<br>
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31<br>
; CHECK: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr14<br>
; CHECK: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr13<br>
; CHECK: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr12<br>
<br>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir<br>
index 395d34a00081..8798e9f85826 100644<br>
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir<br>
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir<br>
@@ -171,7 +171,7 @@ body: |<br>
liveins: $vgpr0<br>
<br>
; VI-LABEL: name: test_addrspacecast_p5_to_p0<br>
- ; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5<br>
+ ; VI: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5<br>
; VI: [[COPY1:%[0-9]+]]:_(p5) = COPY $vgpr0<br>
; VI: [[C:%[0-9]+]]:_(p5) = G_CONSTANT i32 -1<br>
; VI: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0<br>
@@ -254,7 +254,7 @@ body: |<br>
liveins: $vgpr0<br>
<br>
; VI-LABEL: name: test_addrspacecast_p3_to_p0<br>
- ; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5<br>
+ ; VI: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5<br>
; VI: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr0<br>
; VI: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1<br>
; VI: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0<br>
@@ -459,7 +459,7 @@ body: |<br>
liveins: $vgpr0_vgpr1<br>
<br>
; VI-LABEL: name: test_addrspacecast_v2p3_to_v2p0<br>
- ; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5<br>
+ ; VI: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5<br>
; VI: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1<br>
; VI: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY1]](<2 x p3>)<br>
; VI: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1<br>
<br>
<br>
<br>
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